Study of Correlation of Testability Aspects of RTL Description and Resulting Structural Implementations. - Pradip A. Thaker; Mona E. Zaghloul; Minesh B. Amin (VLSI Design, 1999)

Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (VTS, 1999)

Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (ITC, 2000)

A test evaluation technique for VLSI circuits using register-transfer level fault modeling. - Pradip A. Thaker; Vishwani D. Agrawal; Mona E. Zaghloul (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Holistic verification: myth or magic bullet? - Pradip A. Thaker (DAC, 2009)