Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. - Lakshmanan Balasubramanian; Puneet Sabbarwal; Rajesh Kumar Mittal; Prakash Narayanan; Ranjit Kumar Dash; Anand Devendra Kudari; Srikanth Manian; Sudhir Polarouthu; Harikrishna Parthasarathy; Ravi C. Vijayaraghavan; Sachin Turkewadikar (DATE, 2011)

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. - Rajesh Mittal; Lakshmanan Balasubramanian; Adesh Sontakke; Harikrishna Parthasarathy; Prakash Narayanan; Puneet Sabbarwal; Rubin A. Parekhji (ITC, 2011)

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. - Prakash Narayanan; Rajesh Mittal; Sumanth Poddutur; Vivek Singhal; Puneet Sabbarwal (VTS, 2011)

Novel self-test methods to reduce on-chip memory requirements and improved test coverage. - Prakash Narayanan; Satish Ravichandran; Balaji Ramayanam (IOLTS, 2014)

An optimised SDD ATPG and SDQL computation method across different pattern sets. - Wilson Pradeep; Prakash Narayanan; Rubin A. Parekhji (VTS, 2017)

High-Performance and Small Form-Factor mm-Wave CMOS Radars for Automotive and Industrial Sensing in 76-to-81GHz and 57-to-64GHz Bands. - Krishnanshu Dandu; Sreekiran Samala; Karan Bhatia; Meysam Moallem; Karthik Subburaj; Zeshan Ahmad; Daniel Breen; Sunhwan Jang; Tim Davis; Mayank Singh 010; Shankar Ram; Vashishth Dudhia; et al. (ISSCC, 2021)