Effective communication in ad hoc network of mobile users group. - Prafulla Kumar Behera; Pramod Kumar Meher (APCCAS (2), 2002)

Reconfigurable execution core for high performance DSP applications. - A. K. Rath; Pramod Kumar Meher (APCCAS (2), 2002)

Prospects of Group-Based Communication in Mobile Ad hoc Networks. - Prafulla Kumar Behera; Pramod Kumar Meher (IWDC, 2002)

Low-Power Transform-Domain Coding by Separable Two-Dimensional Hartley-Like Transform. - Pramod Kumar Meher; Thambipillai Srikanthan; M. Mahesh Kumar; S. Arunkumar (Embedded Systems and Applications, 2003)

WAP-teletext system. - Nadarajah Sriskanthan; Pramod Kumar Meher; Geok See Ng; C. K. Heng (IEEE Trans. Consumer Electron., 2004)

Area-Time Efficient Systolic Architecture for the DCT. - Pramod Kumar Meher (Asia-Pacific Computer Systems Architecture Conference, 2005)

Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 2-D Systolic Array for High-Throughput Computation of 2-D Discrete Fourier Transform. - Pramod Kumar Meher; Jagdish Chandra Patra; A. Prasad Vinod 001 (APCCAS, 2006)

Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform. - Pramod Kumar Meher; A. Prasad Vinod 001; Jagdish Chandra Patra; M. N. S. Swamy (APCCAS, 2006)

VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT. - Basant K. Mohanty; Pramod Kumar Meher (APCCAS, 2006)

Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform. - Basant K. Mohanty; Pramod Kumar Meher (APCCAS, 2006)

An Improved SVD-Based Watermarking Technique for Image and Document Authentication. - Jagdish Chandra Patra; W. Soh; Ee Luang Ang; Pramod Kumar Meher (APCCAS, 2006)

Low Power FIR Filter Realization using Minimal Difference Coefficients: Part I - Complexity Analysis. - A. Prasad Vinod 001; Chip-Hong Chang; Pramod Kumar Meher; Ankita Singla (APCCAS, 2006)

Low Power FIR Filter Realization Using Minimal Difference Coefficients: Part II - Algorithm. - A. Prasad Vinod 001; Chip-Hong Chang; Pramod Kumar Meher; Ankita Singla (APCCAS, 2006)

Field Programmable Gate Array Implementation of a Neural Network-based Intelligent Sensor System. - Jagdish Chandra Patra; Han Yang Lee; Pramod Kumar Meher; Ee Luang Ang (ICARCV, 2006)

A New SOM-based Visualization Technique for DNA Microarray Data. - Jagdish Chandra Patra; Ee Luang Ang; Pramod Kumar Meher; Qin Zhen (IJCNN, 2006)

Financial Prediction of Major Indices using Computational Efficient Artificial Neural Networks. - Jagdish Chandra Patra; Weineng Lim; Pramod Kumar Meher; Ee Luang Ang (IJCNN, 2006)

A new approach to secure distributed storage, sharing and dissemination of digital image. - Pramod Kumar Meher; Jagdish Chandra Patra (ISCAS, 2006)

Low-complexity technique for secure storage and sharing of biomedical images. - Pramod Kumar Meher; Jagdish Chandra Patra; M. R. Meher (ISCAS, 2006)

A novel neural network-based linearization and auto-compensation technique for sensors. - Jagdish Chandra Patra; Ee Luang Ang; Pramod Kumar Meher (ISCAS, 2006)

Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform. - Pramod Kumar Meher (IEEE Signal Process. Lett., 2006)

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Scalable and modular memory-based systolic architectures for discrete Hartley transform. - Pramod Kumar Meher; Thambipillai Srikanthan; Jagdish Chandra Patra (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Systolic Designs for DCT Using a Low-Complexity Concurrent Convolutional Formulation. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2006)

Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2m). - Pramod Kumar Meher (ASAP, 2007)

DNA Microarray Data Analysis: Effective Feature Selection for Accurate Cancer Classification. - Jagdish Chandra Patra; Goh P. Lim; Pramod Kumar Meher; Ee Luang Ang (IJCNN, 2007)

High-Throughput Memory-Based Architecture for DHT Using a New Convolutional Formulation. - Pramod Kumar Meher; Jagdish Chandra Patra; M. N. S. Swamy (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform. - Pramod Kumar Meher; M. N. S. Swamy (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Efficient Bit-Parallel Multipliers in Composite Fields. - Chiou-Yng Lee; Pramod Kumar Meher (APSCC, 2008)

Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms. - Pramod Kumar Meher (ASAP, 2008)

Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. - Pramod Kumar Meher; Jagdish Chandra Patra (ASAP, 2008)

Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform. - Basant K. Mohanty; Pramod Kumar Meher (ASAP, 2008)

Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder. - Basant K. Mohanty; Pramod Kumar Meher (ASAP, 2008)

Discrete tchebichef transform-A fast 4x4 algorithm and its application in image/video compression. - Sujata Ishwar; Pramod Kumar Meher; M. N. S. Swamy (ISCAS, 2008)

Determination of QSAR of aldose reductase inhibitors using an RBF network. - Jagdish Chandra Patra; Rowena Wai Sim Cheong; Pramod Kumar Meher; Goutam Chakraborty (SMC, 2008)

Legendre-FLANN-based nonlinear channel equalization in wireless communication system. - Jagdish Chandra Patra; Wei Chiat Chin; Pramod Kumar Meher; Goutam Chakraborty (SMC, 2008)

Robust CRT-based watermarking technique for authentication of image and document. - Jagdish Chandra Patra; Alagappan Karthik; Pramod Kumar Meher; Cédric Bornand (SMC, 2008)

Support vector machine application in drug discovery of aldose reductase inhibitors. - Jagdish Chandra Patra; Li Li; Pramod Kumar Meher (SMC, 2008)

Development of intelligent sensors using Legendre functional-link artificial neural networks. - Jagdish Chandra Patra; Pramod Kumar Meher; Goutam Chakraborty (SMC, 2008)

Content-based image retrieval using orthogonal moments heuristically. - Jagdish Chandra Patra; Sonaabh Sood; Pramod Kumar Meher; Cédric Bornand (SMC, 2008)

WMicaD: A New Digital Watermarking Technique Using Independent Component Analysis. - Thang Viet Nguyen; Jagdish Chandra Patra; Pramod Kumar Meher (EURASIP J. Adv. Signal Process., 2008)

New Approach to Scalable Parallel and Pipelined Realization of Repetitive Multiple Accumulations. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Systolic and Super-Systolic Multipliers for Finite Field GF(2m) Based on Irreducible Trinomials. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform. - Pramod Kumar Meher; Basant K. Mohanty; Jagdish Chandra Patra (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences. - Jagdish Chandra Patra; Goutam Chakraborty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Parallel and Pipelined Architectures for Cyclic Convolution by Block Circulant Formulation Using Low-Complexity Short-Length Algorithms. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2008)

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic. - Pramod Kumar Meher; Shrutisagar Chandrasekaran; Abbes Amira (IEEE Trans. Signal Process., 2008)

An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. - Pramod Kumar Meher; Yajun Ha; Chiou-Yng Lee (ASP-DAC, 2009)

Computationally efficient FLANN-based intelligent stock price prediction system. - Jagdish Chandra Patra; Nguyen C. Thanh; Pramod Kumar Meher (IJCNN, 2009)

New Approach to LUT Implementation and Accumulation for Memory-based Multiplication. - Pramod Kumar Meher (ISCAS, 2009)

Scalable Serial-parallel Multiplier over GF(2m) by Hierarchical Pre-reduction and Input Decomposition. - Pramod Kumar Meher; Chiou-Yng Lee (ISCAS, 2009)

Nonlinear channel equalization for wireless communication systems using Legendre neural networks. - Jagdish Chandra Patra; Pramod Kumar Meher; Goutam Chakraborty (Signal Process., 2009)

Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications. - Pramod Kumar Meher (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

50 Years of CORDIC: Algorithms, Architectures, and Applications. - Pramod Kumar Meher; Javier Valls; Tso-Bing Juang; K. Sridharan 001; Koushik Maharatna (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation. - Leena Vachhani; K. Sridharan 001; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration. - Leena Vachhani; K. Sridharan 001; Pramod Kumar Meher (IEEE Trans. Ind. Electron., 2009)

On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and its Applications. - Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec. - Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Area-efficient parallel-prefix Ling adders. - Tso-Bing Juang; Pramod Kumar Meher; Chung-Chun Kuan (APCCAS, 2010)

An improved SOM-based visualization technique for DNA microarray data analysis. - Jagdish Chandra Patra; Jacob A. Abraham; Pramod Kumar Meher; Goutam Chakraborty (IJCNN, 2010)

DNA microarray analysis using Equalized Orthogonal Mapping. - Jagdish Chandra Patra; Nyttle V. George; Pramod Kumar Meher (IJCNN, 2010)

An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks. - Pramod Kumar Meher (VLSI-SoC, 2010)

Novel input coding technique for high-precision LUT-based multiplication for DSP applications. - Pramod Kumar Meher (VLSI-SoC, 2010)

Efficient bit-parallel multipliers over finite fields GF(2m). - Chiou-Yng Lee; Pramod Kumar Meher (Comput. Electr. Eng., 2010)

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. - Achutavarrier Prasad Vinod; Edmund Ming-Kit Lai; Douglas L. Maskell; Pramod Kumar Meher (Integr., 2010)

New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

LUT Optimization for Memory-Based Computation. - Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2010)

Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2m) Using Multiple Parity Prediction Schemes. - Chiou-Yng Lee; Pramod Kumar Meher; Jagdish Chandra Patra (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications. - Pramod Kumar Meher; Jagdish Chandra Patra; Achutavarrier Prasad Vinod (J. Signal Process. Syst., 2010)

Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula. - Chiou-Yng Lee; Pramod Kumar Meher (ICGEC, 2011)

A high-speed FIR adaptive filter architecture using a modified delayed LMS algorithm. - Pramod Kumar Meher; Megha Maheshwari (ISCAS, 2011)

Efficient coefficient partitioning for decomposed DA-based inner-product computation. - Yu Pan; Pramod Kumar Meher (ISCAS, 2011)

A New Look-Up Table Approach for High-Speed Finite Field Multiplication. - Bimal Kumar Meher; Pramod Kumar Meher (ISED, 2011)

MCM-based implementation of block FIR filters for high-speed and low-power applications. - Pramod Kumar Meher; Yu Pan (VLSI-SoC, 2011)

High-throughput pipelined realization of adaptive FIR filter based on distributed arithmetic. - Pramod Kumar Meher; Sang Yoon Park (VLSI-SoC, 2011)

High-Speed RS(255, 239) Decoder Based on LCC Decoding. - Francisco Garcia-Herrero; Javier Valls; Pramod Kumar Meher (Circuits Syst. Signal Process., 2011)

Guest Editorial: Special Issue on Embedded Signal Processing Circuits and Systems for Cognitive Radio-Based Wireless Communication Devices. - A. Prasad Vinod 001; Edmund Ming-Kit Lai; Pramod Kumar Meher; Jacques Palicot; Shahriar Mirabbasi (Circuits Syst. Signal Process., 2011)

Improved Comb Filter based Approach for Effective Prediction of Protein Coding Regions in DNA Sequences. - Jayakishan Meher; Pramod Kumar Meher; Gananath Dash (J. Signal Inf. Process., 2011)

The Role of Combined OSR and SDF Method for Pre-Processing of Microarray Data that Accounts for Effective Denoising and Quantification. - Jayakishan Meher; Mukesh Kumar Raval; Pramod Kumar Meher; Gananath Dash (J. Signal Inf. Process., 2011)

A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network. - Natarajan Sudha; A. R. Mohan; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2011)

Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks. - Jagdish Chandra Patra; Pramod Kumar Meher; Goutam Chakraborty (IEEE Trans. Instrum. Meas., 2011)

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2011)

Memory-Efficient Architecture for 3-D DWT Using Overlapped Grouping of Frames. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2011)

A low-complexity spectrum sensing technique for cognitive radios based on correlation of intra-segment decimated vectors. - Syed Naveen Altaf Ahmed; Pramod Kumar Meher; A. Prasad Vinod 001 (ICCS, 2012)

Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform. - Basant K. Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal (ISCAS, 2012)

Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (ISCAS, 2012)

New encoded single-indicator sequences based on physico-chemical parameters for efficient exon identification. - Jayakishan Meher; Pramod Kumar Meher; Gananath Dash; Mukesh Kumar Raval (Int. J. Bioinform. Res. Appl., 2012)

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT. - Basant K. Mohanty; Anurag Mahajan; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Very Large Scale Integr. Syst., 2012)

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. - Francisco Garcia-Herrero; María José Canet; Javier Valls; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression. - Maher Jridi; Ayman Alfalou; Pramod Kumar Meher (VLSI Design, 2012)

A variable quantization technique for image compression using integer Tchebichef transform. - Soni Prattipati; M. N. S. Swamy; Pramod Kumar Meher (ICICS, 2013)

Flexible integer DCT architectures for HEVC. - Sang Yoon Park; Pramod Kumar Meher (ISCAS, 2013)

A fast 8×8 integer Tchebichef transform and comparison with integer cosine transform for image compression. - Soni Prattipati; Sujata Ishwar; M. N. S. Swamy; Pramod Kumar Meher (MWSCAS, 2013)

An Efficient Look-up Table-based Approach for Multiplication over GF(2m) Generated by Trinomials. - Bimal Kumar Meher; Pramod Kumar Meher (Circuits Syst. Signal Process., 2013)

Guest Editorial: Advanced Techniques for Efficient Electronic System Design. - Pramod Kumar Meher; Saraju P. Mohanty; A. Prasad Vinod 001 (Circuits Syst. Signal Process., 2013)

Zero-quantised discrete cosine transform coefficients prediction technique for intra-frame video encoding. - Maher Jridi; Pramod Kumar Meher; Ayman Alfalou (IET Image Process., 2013)

Special section on image and video processing for security. - Natarajan Sudha; Niladri B. Puhan; Pramod Kumar Meher (Signal Image Video Process., 2013)

Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (IEEE Trans. Computers, 2013)

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields. - Jeng-Shyang Pan 001; Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic. - Sang Yoon Park; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Memory-Efficient High-Speed Convolution-Based Generic Structure for Multilevel 2-D DWT. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2013)

A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Signal Process., 2013)

CORDIC Designs for Fixed Angle of Rotation. - Pramod Kumar Meher; Sang Yoon Park (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. - Jiafeng Xie; Jianjun He; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. - Jiafeng Xie; Pramod Kumar Meher; Jianjun He (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Reconfigurable CORDIC architectures for multi-mode and multi-trajectory operations. - Supriya Aggarwal; Pramod Kumar Meher (ISCAS, 2014)

High-speed multiplier block design based on bit-level critical path optimization. - Xin Lou; Ya Jun Yu; Pramod Kumar Meher (ISCAS, 2014)

Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. - Pramod Kumar Meher; Basant K. Mohanty; Thambipillai Srikanthan (ISCAS, 2014)

A novel DA-based architecture for efficient computation of inner-product of variable vectors. - Pramod Kumar Meher; Sang Yoon Park (ISCAS, 2014)

Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. - Chiou-Yng Lee; Pramod Kumar Meher; Wen-Yo Lee (ISIC, 2014)

Area-delay-power-efficient architecture for folded two-dimensional discrete wavelet transform by multiple lifting computation. - Basant K. Mohanty; Pramod Kumar Meher (IET Image Process., 2014)

Efficient $M$ -ary Exponentiation over $GF(2^{m})$ Using Subquadratic KA-Based Three-Operand Montgomery Multiplier. - Chiou-Yng Lee; Pramod Kumar Meher; Chien-Ping Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Complexity Digit-Serial and Scalable SPB/GPB Multipliers Over Large Binary Extension Fields Using (b, 2)-Way Karatsuba Decomposition. - Chiou-Yng Lee; Chun-Sheng Yang; Bimal Kumar Meher; Pramod Kumar Meher; Jeng-Shyang Pan 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm. - Pramod Kumar Meher; Sang Yoon Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters. - Basant K. Mohanty; Pramod Kumar Meher; Somaya Al-Máadeed; Abbes Amira (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation. - Yu Pan; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter. - Sang Yoon Park; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Efficient Integer DCT Architectures for HEVC. - Pramod Kumar Meher; Sang Yoon Park; Basant Kumar Mohanty; Khoon Seong Lim; Chuohao Yeo (IEEE Trans. Circuits Syst. Video Technol., 2014)

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay. - Pramod Kumar Meher; Sang Yoon Park (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fine-grained pipelining for multiple constant multiplications. - Xin Lou; Pramod Kumar Meher; Ya Jun Yu (ISCAS, 2015)

Critical-path optimization for efficient hardware realization of lifting and flipping DWTs. - Basant K. Mohanty; Pramod Kumar Meher; Thambipillai Srikanthan (ISCAS, 2015)

Efficient subquadratic parallel multiplier based on modified SPB of GF(2m). - Jeng-Shyang Pan 001; Pramod Kumar Meher; Chiou-Yng Lee; Hong-Hai Bai (ISCAS, 2015)

Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters. - Pramod Kumar Meher; Basant Kumar Mohanty; M. N. S. Swamy (VLSID, 2015)

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. - Shen-Fu Hsiao; Po-Han Wu; Chia-Sheng Wen; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT. - Maher Jridi; Ayman Alfalou; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2m) Using Symmetric TMVP and Block Recombination Techniques. - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach. - Chung-Hsin Liu; Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple Constant Multiplications. - Xin Lou; Ya Jun Yu; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications. - Xin Lou; Ya Jun Yu; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data. - Pramod Kumar Meher; Basant Kumar Mohanty; Sujit Kumar Patel; Soumya Ganguly; Thambipillai Srikanthan (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Low-Latency High-Throughput Systolic Multipliers Over GF(2m) for NIST Recommended Pentanomials. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

High-Throughput Digit-Level Systolic Multiplier Over GF(2m) Based on Irreducible Trinomials. - Jiafeng Xie; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction. - Hassan Rabah; Abbes Amira; Basant Kumar Mohanty; Somaya Al-Máadeed; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Seamless Pipelining of DSP Circuits. - Pramod Kumar Meher (Circuits Syst. Signal Process., 2016)

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic. - Basant Kumar Mohanty; Pramod Kumar Meher; Subodh Kumar Singhal; M. N. S. Swamy (Integr., 2016)

Comment on "Subquadratic Space-Complexity Digit-Serial Multipliers Over GF(2m) Using Generalized (a, b)-Way Karatsuba Algorithm". - Chiou-Yng Lee; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. - Xin Lou; Ya Jun Yu; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Introduction of New Associate Editors. - Nikolaos V. Boulgouris; David R. Bull; Marco Cagnazzo; Andrea Cavallaro; Gene Cheung; Amit K. Roy-Chowdhury; Pedro Comesaña Alfaro; Shan Du; Sarp Ertürk; Markus Flierl; Gian Luca Foresti; Gang Hua 001; et al. (IEEE Trans. Circuits Syst. Video Technol., 2016)

Concept, Design, and Implementation of Reconfigurable CORDIC. - Supriya Aggarwal; Pramod Kumar Meher; Kavita Khare (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach. - Chiou-Yng Lee; Pramod Kumar Meher; Chung-Hsin Liu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

On Efficient Retiming of Fixed-Point Circuits. - Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. - Basant Kumar Mohanty; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2016)

LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter. - Basant K. Mohanty; Pramod Kumar Meher; Sujit Kumar Patel (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Lookup Table-Based Low-Power Implementation of Multi-channel Filters for Software Defined Radio. - Subhendu Kumar Sahoo; Pramod Kumar Meher (iNIS, 2017)

Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications. - Xin Lou; Ya Jun Yu; Pramod Kumar Meher (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Novel Structure for Area-Efficient Implementation of FIR Filters. - Xin Lou; Pramod Kumar Meher; Yajun Yu; Wenbin Ye 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials. - Pramod Kumar Meher; Xin Lou (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2m) Based on NIST Polynomials. - Jiafeng Xie; Pramod Kumar Meher; Mingui Sun; Yuecheng Li; Bo Zeng 001; Zhi-Hong Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding. - Maher Jridi; Pramod Kumar Meher (IEEE Trans. Circuits Syst. Video Technol., 2017)

Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition. - Chiou-Yng Lee; Pramod Kumar Meher; Chia-Chen Fan; Shyan-Ming Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient Cross-Correlation Algorithm and Architecture for Robust Synchronization in Frame-Based Communication Systems. - Syed Naveen Altaf Ahmed; Pramod Kumar Meher; Achutavarrier Prasad Vinod (Circuits Syst. Signal Process., 2018)

Efficient Shift-Add Implementation of FIR Filters Using Variable Partition Hybrid Form Structures. - Dwaipayan Ray; Nithin V. George; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Threshold-Guided Design and Optimization for Harris Corner Detector Architecture. - Bhavan A. Jasani; Siew-Kei Lam; Pramod Kumar Meher; Meiqing Wu (IEEE Trans. Circuits Syst. Video Technol., 2018)

Low Register-Complexity Systolic Digit-Serial Multiplier Over GF(2m) Based on Trinomials. - Jiafeng Xie; Pramod Kumar Meher; Xiaojun Zhou; Chiou-Yng Lee (IEEE Trans. Multi Scale Comput. Syst., 2018)

Analysis and Design of Approximate Inner-Product Architectures Based on Distributed Arithmetic. - Dwaipayan Ray; Nithin V. George; Pramod Kumar Meher (ISCAS, 2019)

Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher (ISCAS, 2019)

Low Latency Scaling-Free Pipeline CORDIC Architecture Using Augmented Taylor Series. - Sumit Satyavijay Wadkar; Bishnu Prasad Das; Pramod Kumar Meher (iSES, 2019)

Multichannel Filters for Wireless Networks: Lookup-Table-Based Efficient Implementation. - Subhendu Kumar Sahoo; Pramod Kumar Meher; Ganesh Kumar Ganjikunta (IEEE Consumer Electron. Mag., 2019)

50 Years of FFT Algorithms and Applications. - G. Ganesh Kumar; Subhendu Kumar Sahoo; Pramod Kumar Meher (Circuits Syst. Signal Process., 2019)

Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields. - Bimal Kumar Meher; Pramod Kumar Meher (Circuits Syst. Signal Process., 2019)

Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data. - Basant K. Mohanty; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. - Jiafeng Xie; Chiou-Yng Lee; Pramod Kumar Meher; Zhi-Hong Mao (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Efficient approximate core transform and its reconfigurable architectures for HEVC. - Maher Jridi; Ayman Alfalou; Pramod Kumar Meher (J. Real Time Image Process., 2020)

An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures. - Dwaipayan Ray; Nithin V. George; Pramod Kumar Meher (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. - Basant Kumar Mohanty; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters. - Dwaipayan Ray; Nithin V. George; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design of Very High-Speed Pipeline FIR Filter Through Precise Critical Path Analysis. - Su Min Cho; Pramod Kumar Meher; Luong Tran Nhat Trung; Hyo Jin Cho; Sang Yoon Park (IEEE Access, 2021)

Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design. - Sun Sik Lee; Thanh Dat Nguyen; Pramod Kumar Meher; Sang Yoon Park (IEEE Access, 2022)

Enhanced Sharpening of CIC Decimation Filters, Implementation and Applications. - Supriya Aggarwal; Pramod Kumar Meher (Circuits Syst. Signal Process., 2022)

Dense-PSP-UNet: A neural network for fast inference liver ultrasound segmentation. - Mohammed Yusuf Ansari; Yin Yang; Pramod Kumar Meher; Sarada Prasad Dakua (Comput. Biol. Medicine, 2023)

An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation. - Anu Verma; Khyati Kiyawat; Bishnu Prasad Das; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors. - Anil Kali; Samrat L. Sabat; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors. - Anil Kali; Samrat L. Sabat; Pramod Kumar Meher (ISCAS, 2024)

Efficient Implementation of Entity On-Boarding and Authentication in Zero-Trust Systems. - Jayashree Rana; Pramod Kumar Meher; Rojalina Priyadarshini; K. Pratyush Rao (PKIA, 2024)

Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. - Srikant Kumar Beura; Bishnulatpam Pushpa Devi; Prabir Saha; Pramod Kumar Meher (Circuits Syst. Signal Process., 2024)

Advancements in Deep Learning for B-Mode Ultrasound Segmentation: A Comprehensive Review. - Mohammed Yusuf Ansari; Iffa Afsa Changaai Mangalote; Pramod Kumar Meher; Omar Aboumarzouk; Abdulla Al-Ansari; Osama Halabi; Sarada Prasad Dakua (IEEE Trans. Emerg. Top. Comput. Intell., 2024)

Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments. - Shouharda Ghosh; Pramod Kumar Meher; Dwaipayan Ray; Nithin V. George (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Input-Output Scheduling and Control for Efficient FPGA Realization of Digit-Serial Multiplication Over Generic Binary Extension Fields. - Dibakar Pradhan; Pramod Kumar Meher; Bimal Kumar Meher (Circuits Syst. Signal Process., 2024)

FPGA-Specific Efficient Designs of Digit-Serial Multiplier for Galois Field GF(2m). - Dibakar Pradhan; Pramod Kumar Meher; Bimal Kumar Meher (Circuits Syst. Signal Process., 2025)

A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors. - Anil Kali; Samrat L. Sabat; Pramod Kumar Meher (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Efficient Design and Implementation of Scale-Free CORDIC With Mutually Exclusive Micro-Rotations. - Pramod Kumar Meher; Supriya Aggarwal (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)