Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. - Prasenjit Biswas; Pramod P. Udupa; Rajdeep Mondal; Keshavan Varadarajan; Mythri Alle; S. K. Nandy 001; Ranjani Narayan (ISVLSI, 2010)

A hardware accelerated system for deep packet inspection. - Adarsha Rao; Pramod P. Udupa (MEMOCODE, 2010)

A block-parallel architecture for initial and fine synchronization in OFDM systems. - Pramod P. Udupa; Olivier Sentieys; Pascal Scalart (ICC, 2013)

A Novel Hierarchical Low Complexity Synchronization Method for OFDM Systems. - Pramod P. Udupa; Olivier Sentieys; Pascal Scalart (VTC Spring, 2013)

Accelerating Depthwise Convolution and Pooling Operations on z-First Storage CNN Architectures. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (ISCAS, 2020)

IKW: Inter-Kernel Weights for Power Efficient Edge Computing. - Pramod P. Udupa; Gopinath Mahale; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Access, 2020)

WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices. - Gopinath Mahale; Pramod P. Udupa; Kiran Kolar Chandrasekharan; Sehwan Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)