Magnitude locked loop. - K. Radhakrishna Rao; Pranav Ashar (Proc. IEEE, 1988)

Optimum and heuristic algorithms for finite state machine decomposition and partitioning. - Pranav Ashar; Srinivas Devadas; A. Richard Newton (ICCAD, 1989)

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. - Pranav Ashar; Srinivas Devadas; A. Richard Newton (DAC, 1990)

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. - Pranav Ashar; Abhijit Ghosh; Srinivas Devadas; A. Richard Newton (ICCAD, 1990)

Testability driven synthesis of interacting finite state machines. - Pranav Ashar; Srinivas Devadas; A. Richard Newton (ICCD, 1990)

Optimum and heuristic algorithms for an approach to finite state machine decomposition. - Pranav Ashar; Srinivas Devadas; A. Richard Newton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Irredundant interacting sequential machines via optimal logic synthesis. - Pranav Ashar; Srinivas Devadas; A. Richard Newton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Exploiting multi-cycle false paths in the performance optimization of sequential circuits. - Pranav Ashar; Sujit Dey; Sharad Malik (ICCAD, 1992)

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams. - Pranav Ashar; Abhijit Ghosh; Srinivas Devadas (Integr., 1992)

Technology Mapping for Lower Power. - Vivek Tiwari; Pranav Ashar; Sharad Malik (DAC, 1993)

Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. - Pranav Ashar; Srinivas Devadas; Kurt Keutzer (Formal Methods Syst. Des., 1993)

Path-delay-fault testability properties of multiplexor-based networks. - Pranav Ashar; Srinivas Devadas; Kurt Keutzer (Integr., 1993)

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. - Pranav Ashar; Sharad Malik (DAC, 1994)

Efficient breadth-first manipulation of binary decision diagrams. - Pranav Ashar; Matthew Cheong (ICCAD, 1994)

Fast functional simulation using branching programs. - Pranav Ashar; Sharad Malik (ICCAD, 1995)

Exploiting multicycle false paths in the performance optimization of sequential logic circuits. - Pranav Ashar; Sujit Dey; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Functional timing analysis using ATPG. - Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Test generation for cyclic combinational circuits. - Anand Raghunathan; Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Scheduling Techniques to Enable Power Management. - José Monteiro 001; Srinivas Devadas; Pranav Ashar; Ashutosh Mauskar (DAC, 1996)

Technology mapping for low power in logic synthesis. - Vivek Tiwari; Pranav Ashar; Sharad Malik (Integr., 1996)

Toward Formalizing a Validation Methodology Using Simulation Coverage. - Aarti Gupta; Sharad Malik; Pranav Ashar (DAC, 1997)

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. - Peixin Zhong; Pranav Ashar; Sharad Malik; Margaret Martonosi (DAC, 1998)

Accelerating Boolean Satisfiability with Configurable Hardware. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (FCCM, 1998)

Solving Boolean Satisfiability with Dynamic Hardware Configurations. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (FPL, 1998)

Verification of RTL generated from scheduled behavior in a high-level synthesis flow. - Pranav Ashar; Subhrajit Bhattacharya; Anand Raghunathan; Akira Mukaiyama (ICCAD, 1998)

Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. - Aarti Gupta; Pranav Ashar (VLSI Design, 1998)

Guarded evaluation: pushing power management to logic synthesis/design. - Vivek Tiwari; Sharad Malik; Pranav Ashar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Exploiting Retiming in a Guided Simulation Based Validation Methodology. - Aarti Gupta; Pranav Ashar; Sharad Malik (CHARME, 1999)

Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. - Farzan Fallah; Pranav Ashar; Srinivas Devadas (DAC, 1999)

An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. - Zhen Luo; Margaret Martonosi; Pranav Ashar (FCCM, 1999)

Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. - Pranav Ashar; Anand Raghunathan; Aarti Gupta; Subhrajit Bhattacharya (ICCD, 1999)

Using configurable computing to accelerate Boolean satisfiability. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

SAT-Based Image Computation with Application in Reachability Analysis. - Aarti Gupta; Zijiang Yang 006; Pranav Ashar; Anubhav Gupta 001 (FMCAD, 2000)

Fast Error Diagnosis for Combinational Verification. - Aarti Gupta; Pranav Ashar (VLSI Design, 2000)

Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. - Yang Xia; Pranav Ashar (VLSI Design, 2000)

An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking. - Zhen Luo; Margaret Martonosi; Pranav Ashar (VLSI Design, 2000)

Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. - Aarti Gupta; Anubhav Gupta 001; Zijiang Yang 006; Pranav Ashar (DAC, 2001)

Property-specific witness graph generation for guided simulation. - Albert E. Casavant; Aarti Gupta; S. Liu; Akira Mukaiyama; Kazutoshi Wakabayashi; Pranav Ashar (DATE, 2001)

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. - Aarti Gupta; Zijiang Yang 006; Pranav Ashar; Lintao Zhang; Sharad Malik (ICCAD, 2001)

Using complete-1-distinguishability for FSM equivalence checking. - Pranav Ashar; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2001)

A fast, inexpensive and scalable hardware acceleration technique for functional simulation. - Srihari Cadambi; Chandra Mulpuri; Pranav Ashar (DAC, 2002)

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. - Malay K. Ganai; Pranav Ashar; Aarti Gupta; Lintao Zhang; Sharad Malik (DAC, 2002)

Property-Specific Testbench Generation for Guided Simulation. - Aarti Gupta; Albert E. Casavant; Pranav Ashar; Sean Liu; Akira Mukaiyama; Kazutoshi Wakabayashi (ASP-DAC/VLSI Design, 2002)

Functional vector generation for sequential HDL models under an observability-based code coverage metric. - Farzan Fallah; Pranav Ashar; Srinivas Devadas (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Abstraction and BDDs Complement SAT-Based BMC in DiVer. - Aarti Gupta; Malay K. Ganai; Chao Wang 001; Zijiang Yang 006; Pranav Ashar (CAV, 2003)

Learning from BDDs in SAT-based bounded model checking. - Aarti Gupta; Malay K. Ganai; Chao Wang 001; Zijiang Yang 006; Pranav Ashar (DAC, 2003)

Iterative Abstraction using SAT-based BMC with Proof Analysis. - Aarti Gupta; Malay K. Ganai; Zijiang Yang 006; Pranav Ashar (ICCAD, 2003)

Efficient Modeling of Embedded Memories in Bounded Model Checking. - Malay K. Ganai; Aarti Gupta; Pranav Ashar (CAV, 2004)

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. - Malay K. Ganai; Aarti Gupta; Pranav Ashar (ICCAD, 2004)

F-Soft: Software Verification Platform. - Franjo Ivancic; Zijiang Yang 006; Malay K. Ganai; Aarti Gupta; Ilya Shlyakhter; Pranav Ashar (CAV, 2005)

Beyond safety: customized SAT-based model checking. - Malay K. Ganai; Aarti Gupta; Pranav Ashar (DAC, 2005)

Verification of Embedded Memory Systems using Efficient Memory Modeling. - Malay K. Ganai; Aarti Gupta; Pranav Ashar (DATE, 2005)

DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. - Malay K. Ganai; Aarti Gupta; Pranav Ashar (TACAS, 2005)

Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. - Aarti Gupta; Malay K. Ganai; Pranav Ashar (VLSI Design, 2005)

Panel: Assertion-Based Verification -What's the Big Deal? - Sandeep K. Shukla; Alan J. Hu; Jacob Abrahams; Pranav Ashar; Harry Foster; Avner Landver; Carl Pixley (HLDVT, 2006)

Efficient distributed SAT and SAT-based distributed Bounded Model Checking. - Malay K. Ganai; Aarti Gupta; Zijiang Yang 006; Pranav Ashar (Int. J. Softw. Tools Technol. Transf., 2006)

Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. - Aleksandr Zaks; Zijiang Yang 006; Ilya Shlyakhter; Franjo Ivancic; Srihari Cadambi; Malay K. Ganai; Aarti Gupta; Pranav Ashar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Efficient SAT-based bounded model checking for software verification. - Franjo Ivancic; Zijiang Yang 006; Malay K. Ganai; Aarti Gupta; Pranav Ashar (Theor. Comput. Sci., 2008)

Clock domain verification challenges and scalable solutions. - Pranav Ashar (HLDVT, 2010)

Static verification based signoff - A key enabler for managing verification complexity in the modern soc. - Pranav Ashar (FMCAD, 2013)

A paradigm shift in verification methodology. - Pranav Ashar (FMCAD, 2016)

Failures and verification solutions related to untimed paths in SOCs. - Pranav Ashar; Vikas Sachdeva; Vinod Viswanath (ISQED, 2017)

Closing the Verification Gap with Static Sign-off. - Pranav Ashar; Vinod Viswanath (ISQED, 2019)