An efficient approach for design and testing of FPGA programming using Lab VIEW. - B. Naresh Kumar Reddy; N. Suresh; Janjhyam Venkata Naga Ramesh; T. Pavithra; Y. Krupa Bahulya; Pranose J. Edavoor; S. Janaki Ram (ICACCI, 2015)

Poster: An Efficient Low Power & High Performance in MPSOC. - K. Jayasree; B. Naresh Kumar Reddy; B. Srinuvasu Kumar; Janjhyam Venkata Naga Ramesh; Pranose J. Edavoor; Mohd Kashif Zia Ansari (WCI, 2015)

FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. - Pranose J. Edavoor; Sithara Raveendran; Arjun T. V.; Sumesh K. P.; Kumar Y. B. Nithin; M. H. Vasantha (ICCCNT, 2016)

Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. - Priyanandini Das; Pranose J. Edavoor; Sithara Raveendran; Sunil Rathore; Amol D. Rahulkar (ISED, 2017)

Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (ISED, 2017)

Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (TENCON, 2018)

Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank. - Pranose J. Edavoor; Amol D. Rahulkar (IET Image Process., 2019)

Reversible Logic Implementation of Image Denoising for Grayscale Images. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Y. B.; M. H. Vasantha (MWSCAS, 2020)

Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (IEEE Access, 2020)

An Approximate Low-Power Lifting Scheme Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (IEEE Access, 2020)

Design and implementation of image kernels using reversible logic gates. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (IET Image Process., 2020)

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; M. H. Vasantha (IEEE Access, 2021)

A Novel Design of Dyadic db3 Orthogonal Wavelet Filter Bank for Feature Extraction. - Aswini K. Samantaray; Amol D. Rahulkar; Pranose J. Edavoor (Circuits Syst. Signal Process., 2021)

Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (J. Circuits Syst. Comput., 2021)

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Y. B. Nithin Kumar; M. H. Vasantha (ISCAS, 2022)

A Novel Design of Symmetric Daub-4 Wavelet Filter Bank for Image Analysis. - Aswini K. Samantaray; Pranose J. Edavoor; Amol D. Rahulkar (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A New Approach to the Design and Implementation of a Family of Multiplier Free Orthogonal Wavelet Filter Banks. - Aswini K. Samantaray; Pranose J. Edavoor; Amol D. Rahulkar (IEEE Trans. Circuits Syst. Video Technol., 2022)

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. - Pranose J. Edavoor; Aneesh Raveendran; David Selvakumar; Vivian Desalphine; Shankar G. Dharani; Gopal Raut (VLSID, 2023)

Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval. - Aswini K. Samantaray; Pranose J. Edavoor; Amol D. Rahulkar (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A SIMD Dynamic Fixed Point Processing Engine for DNN Accelerators. - Gopal Raut; Pranose J. Edavoor; David Selvakumar; Ritambhara Thakur (ISQED, 2024)

A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. - Aswini K. Samantaray; Pranose J. Edavoor; Amol D. Rahulkar (IEEE Trans. Very Large Scale Integr. Syst., 2024)