On Generating Vectors for Accurate Post-Silicon Delay Characterization. - Prasanjeet Das; Sandeep K. Gupta 001 (Asian Test Symposium, 2011)

Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. - Prasanjeet Das; Sandeep K. Gupta 001 (ICCD, 2013)

Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. - Prasanjeet Das; Sandeep K. Gupta 001 (VTS, 2013)

Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations. - Prasanjeet Das; Sandeep K. Gupta 001 (ISQED, 2014)