Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs. - Prasanth Chatarasi; Vivek Sarkar (PACT, 2015)

Polyhedral Optimizations of Explicitly Parallel Programs. - Prasanth Chatarasi; Jun Shirako; Vivek Sarkar (PACT, 2015)

An Extended Polyhedral Model for SPMD Programs and Its Use in Static Data Race Detection. - Prasanth Chatarasi; Jun Shirako; Martin Kong; Vivek Sarkar (LCPC, 2016)

A Unified Approach to Variable Renaming for Enhanced Vectorization. - Prasanth Chatarasi; Jun Shirako; Albert Cohen 001; Vivek Sarkar (LCPC, 2018)

A Preliminary Study of Compiler Transformations for Graph Applications on the Emu System. - Prasanth Chatarasi; Vivek Sarkar (MCHPC@SC, 2018)

Experimental Insights from the Rogues Gallery. - Jeffrey S. Young 001; E. Jason Riedy; Thomas M. Conte; Vivek Sarkar; Prasanth Chatarasi; Sriseshan Srikanth (ICRC, 2019)

Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. - Hyoukjun Kwon; Prasanth Chatarasi; Michael Pellauer; Angshuman Parashar; Vivek Sarkar; Tushar Krishna (MICRO, 2019)

Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. - Prasanth Chatarasi; Stephen Neuendorffer; Samuel Bayliss; Kees A. Vissers; Vivek Sarkar (HPEC, 2020)

MARVEL: A Decoupled Model-driven Approach for Efficiently Mapping Convolutions on Spatial DNN Accelerators. - Prasanth Chatarasi; Hyoukjun Kwon; Natesh Raina; Saurabh Malik; Vaisakh Haridas; Tushar Krishna; Vivek Sarkar (CoRR, 2020)

MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings. - Hyoukjun Kwon; Prasanth Chatarasi; Vivek Sarkar; Tushar Krishna; Michael Pellauer; Angshuman Parashar (IEEE Micro, 2020)

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators. - Geonhwa Jeong; Gokcen Kestor; Prasanth Chatarasi; Angshuman Parashar; Po-An Tsai; Sivasankaran Rajamanickam; Roberto Gioiosa; Tushar Krishna (PACT, 2021)

Advancing Compiler Optimizations for General-Purpose & Domain-Specific Parallel Architectures. - Prasanth Chatarasi (2021)

Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. - Prasanth Chatarasi; Hyoukjun Kwon; Angshuman Parashar; Michael Pellauer; Tushar Krishna; Vivek Sarkar (ACM Trans. Archit. Code Optim., 2022)

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication. - Gordon Euhyun Moon; Hyoukjun Kwon; Geonhwa Jeong; Prasanth Chatarasi; Sivasankaran Rajamanickam; Tushar Krishna (IEEE Trans. Parallel Distributed Syst., 2022)

FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching. - Jianming Tong; Anirudh Itagi; Prasanth Chatarasi; Tushar Krishna (ISCA, 2024)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)