FLAW: FPGA lifetime awareness. - Suresh Srinivasan; Prasanth Mangalagiri; Yuan Xie 001; Narayanan Vijaykrishnan; Karthik Sarpatwari (DAC, 2006)

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. - Jungsub Kim; Prasanth Mangalagiri; Kevin M. Irick; Mahmut T. Kandemir; Vijaykrishnan Narayanan; Kanwaldeep Sobti; Lanping Deng; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun (FPL, 2007)

FPGA routing architecture analysis under variations. - Suresh Srinivasan; Prasanth Mangalagiri; Yuan Xie 001; Narayanan Vijaykrishnan (ICCD, 2007)

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. - Kanwaldeep Sobti; Lanping Deng; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun; Jungsub Kim; Prasanth Mangalagiri; Kevin M. Irick; Mahmut T. Kandemir; Vijaykrishnan Narayanan (SiPS, 2007)

A low-power phase change memory based hybrid cache architecture. - Prasanth Mangalagiri; Karthik Sarpatwari; Aditya Yanamandra; Vijaykrishnan Narayanan; Yuan Xie 001; Mary Jane Irwin; Osama Awadel Karim (ACM Great Lakes Symposium on VLSI, 2008)

Thermal-aware reliability analysis for platform FPGAs. - Prasanth Mangalagiri; Sungmin Bae; Krishnan Ramakrishnan; Yuan Xie 001; Vijaykrishnan Narayanan (ICCAD, 2008)

Toward Increasing FPGA Lifetime. - Suresh Srinivasan; Krishnan Ramakrishnan; Prasanth Mangalagiri; Yuan Xie 001; Vijaykrishnan Narayanan; Mary Jane Irwin; Karthik Sarpatwari (IEEE Trans. Dependable Secur. Comput., 2008)

Exploiting clock skew scheduling for FPGA. - Sungmin Bae; Prasanth Mangalagiri; Narayanan Vijaykrishnan (DATE, 2009)

Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. - Prasanth Mangalagiri; Vijaykrishnan Narayanan (ISVLSI, 2009)

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. - Jungsub Kim; Lanping Deng; Prasanth Mangalagiri; Kevin M. Irick; Kanwaldeep Sobti; Mahmut T. Kandemir; Vijaykrishnan Narayanan; Chaitali Chakrabarti; Nikos Pitsianis; Xiaobai Sun (IEEE Trans. Computers, 2009)

Analog Layout Synthesis: Are We There Yet? - Prasanth Mangalagiri (ISPD, 2019)

CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. - Prasanth Mangalagiri; Lynn Qian; Farrukh Zafar; Praveen Mosalikanti; Phoebe Chang; Arun Kurian; Vinay Saripalli (DAC, 2024)