NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (DAC, 1993)

Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. - Prasanti Uppaluri; Irith Pomeranz; Sudhakar M. Reddy (FTCS, 1994)

NEST: a nonenumerative test generation method for path delay faults in combinational circuits. - Irith Pomeranz; Sudhakar M. Reddy; Prasanti Uppaluri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

On minimizing the number of test points needed to achieve complete robust path delay fault testability. - Prasanti Uppaluri; Uwe Sparmann; Irith Pomeranz (VTS, 1996)