Error Detect Logic Resulting in Faster Address Generate and Decode for Caches. - Prashant D. Joshi (DFT, 2008)

Guest Editorial. - Prashant D. Joshi; Massimo Violante (J. Electron. Test., 2013)

Region Disjoint Paths in a Class of Optimal Line Graph Networks. - Prashant D. Joshi; Arunabha Sen; Said Hamdioui; Koen Bertels (CSE, 2014)

Security methods in fault tolerant modified line graph based networks. - Prashant D. Joshi; Said Hamdioui (DFT, 2014)

Shortest path reduction in a class of uniform fault tolerant networks. - Prashant D. Joshi; Said Hamdioui (DFT, 2014)

Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures. - Prashant D. Joshi; Said Hamdioui (HPSR, 2014)

Region based containers - A new paradigm for the analysis of fault tolerant networks. - Prashant D. Joshi; Arunabha Sen; D. Frank Hsu; Said Hamdioui; Koen Bertels (DFT, 2017)

Tight Bounds in Message Delays Despite Faults in a Class of Line Digraph Networks. - Prashant D. Joshi; D. Frank Hsu; Arunabha Sen; Said Hamdioui; Koen Bertels (ISPAN-FCST-ISCC, 2017)

High Performance Memory Repair. - Feroze Merchant; Anandraj Devarajan; Anik Basu; David Ashen; Brandon Yelton; Prashant D. Joshi (DFT, 2019)

Validation Challenges in Recent Trends of Power Management in Microprocessors. - Nagabhushan Reddy; Sankaran Menon; Prashant D. Joshi (DFT, 2020)

Aging Effects On Clock Gated Memory Phase Paths. - Amlan Ghosh; Saroj Satapathy; Jaydeep P. Kulkarni; Prashant D. Joshi (DFT, 2022)