Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. - Akhil Garg 001; Prashant Dubey (DFT, 2006)

Built in Defect Prognosis for Embedded Memories. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (DDECS, 2007)

GALS Based Shared Test Architecture for Embedded Memories. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (ISCAS, 2007)

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis. - Prashant Dubey; Akhil Garg 001; Sravan Kumar Bhaskarani (ISVLSI, 2007)

On Chip Jitter Measurement through a High Accuracy TDC. - Akhil Garg 001; Prashant Dubey (ISQED, 2008)

Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time. - Prashant Dubey; Akhil Garg 001; Shashank Mahajan (J. Electron. Test., 2010)

38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS. - Prashant Dubey; Rashmi Agarwal (VLSI Design, 2013)

PODIA: Power Optimization through Differential Imbalanced Amplifier. - Prashant Dubey; Atul Kumar Kashyap; Navneet Gupta; Kaushik Saha (VLSI Design, 2013)

A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist. - Prashant Dubey; Gaurav Ahuja; Vaibhav Verma; Sanjay Kumar Yadav; Amit Khanuja (VLSID, 2014)

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision. - Prashant Dubey; Kritika Aditya; Ankur Srivastava; Amit Khanuja; Jamil Kawa; Thu Nguyen (ISCAS, 2017)