Efficient Management of Dynamic Tables. - Aviezri S. Fraenkel; Edward M. Reingold; Prashant Saxena (Inf. Process. Lett., 1994)

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. - Vamsi Boppana; Prashant Saxena; Prithviraj Banerjee; W. Kent Fuchs; C. L. Liu 001 (Euro-Par, Vol. I, 1996)

A performance-driven layer assignment algorithm for multiple interconnect trees. - Prashant Saxena; C. L. Liu 001 (ICCAD, 1998)

The Retiming and Routing of VLSI Circuits - Prashant Saxena (1998)

Crosstalk Minimization Using Wire Perturbations. - Prashant Saxena; C. L. Liu 001 (DAC, 1999)

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. - Prashant Saxena; Peichen Pan; C. L. Liu 001 (VLSI Design, 1999)

A postprocessing algorithm for crosstalk-driven wire perturbation. - Prashant Saxena; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. - Ki-Wook Kim; Seong-Ook Jung; Prashant Saxena; C. L. Liu 001; Sung-Mo Kang (DAC, 2001)

Optimization of the maximum delay of global interconnects duringlayer assignment. - Prashant Saxena; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A System-Level Solution to Domino Synthesis with 2 GHz Application. - B. Chappell; Xinning Wang; Priyadarsan Patra; Prashant Saxena; J. Vendrell; Satyanarayan Gupta; S. Varadarajan; W. Gomes; S. Hussain; H. Krishnamurthy; M. Venkateshmurthy; S. Jain (ICCD, 2002)

Shield count minimization in congested regions. - Prashant Saxena; Satyanarayan Gupta (ISPD, 2002)

The scaling challenge: can correct-by-construction design help? - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (ISPD, 2003)

On integrating power and signal routing for shield count minimization in congested regions. - Prashant Saxena; Satyanarayan Gupta (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Prashant Saxena; C. L. Liu 001; S.-M. S. Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Realizable parasitic reduction for distributed interconnects using matrix pencil technique. - Janet Meiling Wang; Prashant Saxena; Omar Hafiz; Xing Wang (ASP-DAC, 2004)

Modeling repeaters explicitly within analytical placement. - Prashant Saxena; Bill Halpin (DAC, 2004)

The great interconnect buffering debate: are you a chicken or an ostrich? - Desmond Kirkpatrick; Peter J. Osler; Louis Scheffer; Prashant Saxena; Dennis Sylvester (ISPD, 2004)

A predictive distributed congestion metric and its application to technology mapping. - Rupesh S. Shelar; Sachin S. Sapatnekar; Prashant Saxena; Xinning Wang (ISPD, 2004)

Repeater scaling and its impact on CAD. - Prashant Saxena; Noel Menezes; Pasquale Cocchini; Desmond Kirkpatrick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A perturbation-aware noise convergence methodology for high frequency microprocessors. - Prashant Saxena; Kumar N. Lalgudi; Hans J. Greub; Janet Meiling Wang Roveda (ASP-DAC, 2005)

Net weighting to reduce repeater counts during placement. - Brent Goplen; Prashant Saxena; Sachin S. Sapatnekar (DAC, 2005)

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannal Yang; Prashant Saxena; Vijay Pitchumani (ISCAS (6), 2005)

An efficient technology mapping algorithm targeting routing congestion under delay constraints. - Rupesh S. Shelar; Prashant Saxena; Xinning Wang; Sachin S. Sapatnekar (ISPD, 2005)

A predictive distributed congestion metric with application to technology mapping. - Rupesh S. Shelar; Sachin S. Sapatnekar; Prashant Saxena; Xinning Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

The scaling of interconnect buffer needs. - Prashant Saxena (SLIP, 2006)

On controlling perturbation due to repeaters during quadratic placement. - Prashant Saxena (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. - Rupesh S. Shelar; Prashant Saxena; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Routing Congestion in VLSI Circuits - Estimation and Optimization. - Prashant Saxena; Rupesh S. Shelar; Sachin S. Sapatnekar (Springer, 2007)

Estimation of Routing Congestion. - Rupesh S. Shelar; Prashant Saxena (Handbook of Algorithms for Physical Design Automation, 2008)

On improving optimization effectiveness in interconnect-driven physical synthesis. - Prashant Saxena; Vishal Khandelwal; Changge Qiao; Pei-Hsin Ho; J.-C. Lin; Mahesh A. Iyer (ISPD, 2009)

Guest Editorial. - Gi-Joon Nam; Prashant Saxena (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Multi-mode redundancy removal. - Stephen M. Plaza; Prashant Saxena; Thomas R. Shiple; Pei-Hsin Ho (ISQED, 2011)

Guest Editorial. - Prashant Saxena; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

On pioneering nanometer-era routing problems. - Tong Gao; Prashant Saxena (ISPD, 2012)

Aerie: flexible file-system interfaces to storage-class memory. - Haris Volos 001; Sanketh Nalli; Sankaralingam Panneerselvam; Venkatanathan Varadarajan; Prashant Saxena; Michael M. Swift (EuroSys, 2014)

Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. - Wei-Ting Jonas Chan; Pei-Hsin Ho; Andrew B. Kahng; Prashant Saxena (ISPD, 2017)

Aspects of Isogeometric Analysis with Catmull-Clark Subdivision Surfaces. - Zhaowei Liu; Andrew McBride; Prashant Saxena; Paul Steinmann (CoRR, 2019)

Image GPT with Super Resolution. - Bhumika Shah; Ankita Sinha; Prashant Saxena (FICTA (1), 2021)

Vibration Analysis of Piezoelectric Kirchhoff-Love Shells based on Catmull-Clark Subdivision Surfaces. - Zhaowei Liu; Andrew McBride; Prashant Saxena; Luca Heltai; Yilin Qu; Paul Steinmann (CoRR, 2021)

On the Accuracy of Analog Neural Network Inference Accelerators. - T. Patrick Xiao; Ben Feinberg; Christopher H. Bennett; Venkatraman Prabhakar; Prashant Saxena; Vineet Agrawal; Sapan Agarwal; Matthew J. Marinella (CoRR, 2021)

Computational bifurcation analysis of hyperelastic thin shells. - Zhaowei Liu; Andrew McBride; Abhishek Ghosh; Luca Heltai; Weicheng Huang; Tiantang Yu; Paul Steinmann; Prashant Saxena (CoRR, 2022)

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory. - T. Patrick Xiao; Ben Feinberg; Christopher H. Bennett; Vineet Agrawal; Prashant Saxena; Venkatraman Prabhakar; Krishnaswamy Ramkumar; Harsha Medu; Vijay Raghavan; Ramesh Chettuvetty; Sapan Agarwal; Matthew J. Marinella (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Plane stress finite element modelling of arbitrary compressible hyperelastic materials. - Masoud Ahmadi; Andrew McBride; Paul Steinmann; Prashant Saxena (CoRR, 2024)

Surface stability of a layered magnetoelastic half-space. - Davood Shahsavari; Luis Dorfmann; Prashant Saxena (CoRR, 2025)