Evolutionary Standard Cell Synthesis of Unconventional Designs. - Prashanth H. C.; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2022)

Design and Evaluation of In-Exact Compressor based Approximate Multipliers. - Prashanth H. C.; Soujanya S. R; Bindu G. Gowda; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2022)

SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators. - Prashanth H. C.; Madhav Rao (ICCD, 2022)

Improving Digital Circuit Synthesis of Complex Functions using Binary Weighted Fitness and Variable Mutation Rate in Cartesian Genetic Programming. - Prashanth H. C.; Madhav Rao (IJCCI, 2022)

Design and Evaluation of Performance-efficient SoC-on-FPGA for Cloud-based Healthcare Applications. - Mayank Kabra; Prashanth H. C.; Madhav Rao (NorCAS, 2022)

Design-Space Exploration of Systolic Array for Edge Inferencing Applications. - Prashanth H. C.; Yash Dharmesh Mogal; Madhav Rao (AIMLSystems, 2023)

GCells: A Graph-Search Approach to Design Custom Cells for Computational Subsystems. - Mayank Kabra; Shreyas V. S; Prashanth H. C.; Kedar Deshpande; Madhav Rao (DSD, 2023)

IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit. - Bindu G. Gowda; Prashanth H. C.; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2023)

EBASA: Error Balanced Approximate Systolic Array Architecture Design. - Sai Karthik Nandigama; Bindu G. Gowda; Prashanth H. C.; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2023)

ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers. - Bindu G. Gowda; S. N. Raghava; Prashanth H. C.; Pratyush Nandi; Madhav Rao (ICCD, 2023)

Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs. - Prashanth H. C.; Madhav Rao (IJCCI, 2023)

SQRTLIB : Library of Hardware Square Root Designs. - Prashanth H. C.; Sriniketh S. S; Shrikrishna Hebbar; Chinmaye R; Madhav Rao (ISQED, 2023)

Error Diluted Approximate Multipliers Using Positive And Negative Compressors. - Bindu G. Gowda; Prashanth H. C.; Madhav Rao (ISQED, 2023)

Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA. - Harshita Gupta; Mayank Kabra; Nitin D. Patwari; Prashanth H. C.; Madhav Rao (ISQED, 2023)

eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application. - Mayank Kabra; Prashanth H. C.; Kedar Deshpande; Madhav Rao (ISQED, 2023)

HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD. - Mayank Kabra; Prashanth H. C.; Kedar Deshpande; Madhav Rao (ISQED, 2023)

CellFlow: Automated Standard Cell Design Flow. - Prashanth H. C.; Prashanth Jonna; Madhav Rao (ISVLSI, 2023)

Design-Space Exploration of Multiplier Approximation in CNNs. - S. N. Raghava; Prashanth H. C.; Bindu G. Gowda; Pratyush Nandi; Madhav Rao (ISVLSI, 2023)

Design and Evaluation of Inexact Computation based Systolic Array for Convolution. - Sai Karthik Nandigama; Prashanth H. C.; Madhav Rao (LASCAS, 2023)

Trainable windows for SincNet architecture. - Prashanth H. C.; Madhav Rao; Dhanya Eledath; Ramasubramanian C (EURASIP J. Audio Speech Music. Process., 2023)

Correction: Trainable windows for SincNet architecture. - Prashanth H. C.; Madhav Rao; Dhanya Eledath; V. Ramasubramanian 001 (EURASIP J. Audio Speech Music. Process., 2023)

Performance Analysis of OFA-NAS ResNet Topologies Across Diverse Hardware Compute Units. - Prashanth H. C.; Madhav Rao (ACM Great Lakes Symposium on VLSI, 2024)

Roofline Performance Analysis of DNN Architectures on CPU and GPU Systems. - Prashanth H. C.; Madhav Rao (ISQED, 2024)

Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach. - Bindu G. Gowda; Prashanth H. C.; V. N. Muralidhara; Madhav Rao (ISQED, 2024)

Evaluating Deep Neural Network Performance on Edge Accelerators: A Roofline Model Adopted Benchmarking Approach. - Prashanth H. C.; Madhav Rao (SOCC, 2024)