20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. - Pratap Narayan Singh; Ashish Kumar 001; Chandrajit Debnath; Rakesh Malik (CICC, 2007)

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. - Pratap Narayan Singh; Ashish Kumar 001; Chandrajit Debnath; Rakesh Malik (CICC, 2008)

22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology. - Stéphane Le Tual; Pratap Narayan Singh; Christophe Curis; Pierre Dautriche (ISSCC, 2014)

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. - Ashish Kumar 001; Chandrajit Debnath; Pratap Narayan Singh; Vivek Bhatia; Shivani Chaudhary; Vigyan Jain; Stéphane Le Tual; Rakesh Malik (ESSCIRC, 2016)

A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. - Ashish Kumar 001; Chandrajit Debnath; Pratap Narayan Singh; Vivek Bhatia; Shivani Chaudhary; Vigyan Jain; Stéphane Le Tual; Rakesh Malik (IEEE J. Solid State Circuits, 2017)

A Peak-detector-based Ultra Low Power ECG ASIC for Early Detection of Cardio-Vascular Diseases. - Sidharth Thomas; Jaskirat Singh Virdi; Anshul Verma; Bishnu Prasad Das; Kenichi Okada 001; Pratap Narayan Singh (ISCAS, 2024)