A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. - Nereo Markulic; Pratap Tumkur Renukaswamy; Ewout Martens; Barend van Liempd; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Sehoon Park; Anirudh Kankuppe; Qixian Shi; Piet Wambacq; Jan Craninckx (ISSCC, 2020)

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (IEEE J. Solid State Circuits, 2020)

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. - Pratap Tumkur Renukaswamy; Nereo Markulic; Piet Wambacq; Jan Craninckx (ISCAS, 2021)

A 16GHz, $41 text{kHz}_{ text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. - Pratap Tumkur Renukaswamy; Kristof Vaesen; Nereo Markulic; Veerle Derudder; Dae-Woong Park; Piet Wambacq; Jan Craninckx (ISSCC, 2023)

22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. - Ewout Martens; Adam Cooman; Pratap Tumkur Renukaswamy; Shun Nagata; Sehoon Park; Jorge-Luis Lagos 001; Nereo Markulic; Jan Craninckx (ISSCC, 2024)

A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. - Jorge Lagos 001; Pratap Tumkur Renukaswamy; Nereo Markulic; Ewout Martens; Jan Craninckx (VLSI Technology and Circuits, 2024)

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. - Pratap Tumkur Renukaswamy; Kristof Vaesen; Nereo Markulic; Jan Craninckx (IEEE J. Solid State Circuits, 2024)