Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA. - Sujoy Pandit; Prateek Sikka (ICCCNT, 2018)

High-Level synthesis assisted design and verification framework for automotive radar processors. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2020)

Speed optimal FPGA implementation of the encryption algorithms for telecom applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2020)

High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Comput. Intell., 2021)

Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Circuits Syst. Signal Process., 2021)

Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Microprocess. Microsystems, 2021)

Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis. - Prateek Sikka; Abhijit R. Asati; Chandra Shekhar 001 (Wirel. Pers. Commun., 2022)

Hashed Access Policy-Based Secure Data Transmission Using SDHAK-ECC. - Prateek Sikka (Int. J. Cooperative Inf. Syst., 2022)