Interfacing Cores with On-chip Packet-Switched Networks. - Praveen Bhojwani; Rabi N. Mahapatra (VLSI Design, 2003)

A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems. - Praveen Bhojwani; Rabi N. Mahapatra; Eun Jung Kim 001; Thomas Chen (VLSI Design, 2005)

Core Network Interface Architecture and Latency Constrained On-Chip Communication. - Praveen Bhojwani; Rabi N. Mahapatra (ISQED, 2006)

A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip. - Praveen Bhojwani; Rabi N. Mahapatra (DAC, 2007)

A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications. - Jason D. Lee; Praveen Bhojwani; Rabi N. Mahapatra (HASE, 2007)

SAPP: scalable and adaptable peak power management in nocs. - Praveen Bhojwani; Jason D. Lee; Rabi N. Mahapatra (ISLPED, 2007)

An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs. - Praveen Bhojwani; Rabi N. Mahapatra (ISQED, 2007)

IntellBatt: towards smarter battery design. - Suman Kalyan Mandal; Praveen Bhojwani; Saraju P. Mohanty; Rabi N. Mahapatra (DAC, 2008)

An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. - Jason D. Lee; Nikhil Gupta 004; Praveen Bhojwani; Rabi N. Mahapatra (ISQED, 2008)

Robust Concurrent Online Testing of Network-on-Chip-Based SoCs. - Praveen Bhojwani; Rabi N. Mahapatra (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems. - Jason D. Lee; Rabi N. Mahapatra; Praveen Bhojwani (ICCD, 2009)

IntellBatt: Toward a Smarter Battery. - Suman Kalyan Mandal; Rabi N. Mahapatra; Praveen Bhojwani; Saraju P. Mohanty (Computer, 2010)