Minimizing memory requirements for chain-structured synchronous dataflow programs. - Praveen K. Murthy; Shuvra S. Bhattacharyya; Edward A. Lee (ICASSP (2), 1994)

Converting graphical DSP programs into memory constrained software prototypes. - Shuvra S. Bhattacharyya; Praveen K. Murthy; Edward A. Lee (RSP, 1995)

An extension of multidimensional synchronous dataflow to handle arbitrary sampling lattices. - Praveen K. Murthy; Edward A. Lee (ICASSP, 1996)

Optimized software synthesis for synchronous dataflow. - Shuvra S. Bhattacharyya; Praveen K. Murthy; Edward A. Lee (ASAP, 1997)

APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations. - Shuvra S. Bhattacharyya; Praveen K. Murthy; Edward A. Lee (Des. Autom. Embed. Syst., 1997)

Joint Minimization of Code and Data for Synchronous Dataflow Programs. - Praveen K. Murthy; Shuvra S. Bhattacharyya; Edward A. Lee (Formal Methods Syst. Des., 1997)

Scheduling for Embedded Real-Time Systems. - Felice Balarin; Luciano Lavagno; Praveen K. Murthy; Alberto L. Sangiovanni-Vincentelli (IEEE Des. Test Comput., 1998)

A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications. - Praveen K. Murthy; Shuvra S. Bhattacharyya (ISSS, 1999)

Synthesis of Embedded Software from Synchronous Dataflow Specifications. - Shuvra S. Bhattacharyya; Praveen K. Murthy; Edward A. Lee (J. VLSI Signal Process., 1999)

Shared Memory Implementations of Synchronous Dataflow Specifications. - Praveen K. Murthy; Shuvra S. Bhattacharyya (DATE, 2000)

The CBP parameter - a useful annotation to aid block-diagram compilers for DSP. - Shuvra S. Bhattacharyya; Praveen K. Murthy (ISCAS, 2000)

System canvas: a new design environment for embedded DSP and telecommunication systems. - Praveen K. Murthy; Etan G. Cohen; Steve Rowland (CODES, 2001)

Shared buffer implementations of signal processing systems usinglifetime analysis techniques. - Praveen K. Murthy; Shuvra S. Bhattacharyya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Multidimensional synchronous dataflow. - Praveen K. Murthy; Edward A. Lee (IEEE Trans. Signal Process., 2002)

High level hardware validation using hierarchical message sequence charts. - Praveen K. Murthy; Sreeranga P. Rajan; Koichiro Takayama (HLDVT, 2004)

Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. - Ming-Yung Ko; Praveen K. Murthy; Shuvra S. Bhattacharyya (SCOPES, 2004)

Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications. - Praveen K. Murthy; Shuvra S. Bhattacharyya (ACM Trans. Design Autom. Electr. Syst., 2004)

The CBP Parameter: A Module Characterization Approach for DSP Software Optimization. - Shuvra S. Bhattacharyya; Praveen K. Murthy (J. VLSI Signal Process., 2004)

Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls. - Ming-Yung Ko; Praveen K. Murthy; Shuvra S. Bhattacharyya (ACM Trans. Embed. Comput. Syst., 2007)

Top ten challenges in Big Data security and privacy. - Praveen K. Murthy (ITC, 2014)