Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking. - Nasser A. Kurd; Praveen Mosalikanti; Mark Neidengard; Jonathan Douglas; Rajesh Kumar (IEEE J. Solid State Circuits, 2009)

A Family of 32 nm IA Processors. - Nasser A. Kurd; Subramani Bhamidipati; Christopher Mozak; Jeffrey L. Miller; Praveen Mosalikanti; Timothy M. Wilson; Ali M. El-Husseini; Mark Neidengard; Ramy E. Aly; Mahadev Nemani; Muntaquim Chowdhury; Rajesh Kumar (IEEE J. Solid State Circuits, 2011)

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. - Amr Lotfy; Syed Feruz Syed Farooq; Qi S. Wang; Soner Yaldiz; Praveen Mosalikanti; Nasser A. Kurd (CICC, 2015)

Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell). - Praveen Mosalikanti; Nasser A. Kurd; Christopher Mozak; Takao Oshita (CICC, 2015)

Haswell: A Family of IA 22 nm Processors. - Nasser A. Kurd; Muntaquim Chowdhury; Edward Burton; Thomas P. Thomas; Christopher Mozak; Brent Boswell; Praveen Mosalikanti; Mark Neidengard; Anant Deval; Ashish Khanna; Nasirul Chowdhury; Ravi Rajwar; et al. (IEEE J. Solid State Circuits, 2015)

29.3 80ns Fast-Lock 0.4-to-6.5GHz Clock Generator with Self- Referenced Asynchronous Adaptive Droop Mitigation. - Praveen Mosalikanti; Qi Wang; Kuan-Yueh James Shen; Mark Neidengard; Syed Feruz Syed Farooq; Vaughn Grossnickle; Nasser A. Kurd (ISSCC, 2021)

CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. - Prasanth Mangalagiri; Lynn Qian; Farrukh Zafar; Praveen Mosalikanti; Phoebe Chang; Arun Kurian; Vinay Saripalli (DAC, 2024)