Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application. - Andy Lambrechts; Praveen Raghavan; Anthony Leroy; Guillermo Talavera; Tom Vander Aa; Murali Jayapala; Francky Catthoor; Diederik Verkest; Geert Deconinck; Henk Corporaal; Frédéric Robert; Jordi Carrabina (ASAP, 2005)

Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ESTIMedia, 2005)

Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (DATE, 2006)

Compiler-Driven Leakage Energy Reduction in Banked Register Files. - David Atienza; Praveen Raghavan; José L. Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (PATMOS, 2006)

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism. - Daniele Paolo Scarpazza; Praveen Raghavan; David Novo; Francky Catthoor; Diederik Verkest (PATMOS, 2006)

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors. - Praveen Raghavan; Satyakiran Munaga; Estela Rey Ramos; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (ARCS, 2007)

Locality optimization in wireless applications. - Javed Absar; Min Li 001; Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Arnout Vandecappelle; Francky Catthoor (CODES+ISSS, 2007)

Very wide register: an asymmetric register file organization for low power embedded processors. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest; Henk Corporaal (DATE, 2007)

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. - Praveen Raghavan; José L. Ayala; David Atienza; Francky Catthoor; Giovanni De Micheli; Marisa López-Vallejo (ISCAS, 2007)

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. - Liesbet Van der Perre; Bruno Bougard; Jan Craninckx; Wim Dehaene; Lieven Hollevoet; Murali Jayapala; Pol Marchal; Miguel Miranda; Praveen Raghavan; Thomas Schuster; Piet Wambacq; Francky Catthoor; et al. (ISSCC, 2007)

Semi Custom Design: A Case Study on SIMD Shufflers. - Praveen Raghavan; Nandhavel Sethubalasubramanian; Satyakiran Munaga; Estela Rey Ramos; Murali Jayapala; Oliver Weiss; Francky Catthoor; Diederik Verkest (PATMOS, 2007)

Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals. - Thomas Schuster; Bruno Bougard; Praveen Raghavan; Robert Priewasser; David Novo; Liesbet Van der Perre; Francky Catthoor (SAMOS, 2007)

Energy-aware compilation and hardware design for VLIW embedded systems. - José L. Ayala; Marisa López-Vallejo; David Atienza; Praveen Raghavan; Francky Catthoor; Diederik Verkest (Int. J. Embed. Syst., 2007)

Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ACM Trans. Design Autom. Electr. Syst., 2007)

Operation shuffling over cycle boundaries for low energy L0 clustering. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (ASAP, 2008)

Coffee: COmpiler Framework for Energy-Aware Exploration. - Praveen Raghavan; Andy Lambrechts; Javed Absar; Murali Jayapala; Francky Catthoor; Diederik Verkest (HiPEAC, 2008)

A unified instruction set programmable architecture for multi-standard advanced forward error correction. - Frederik Naessens; Bruno Bougard; Siebert Bressinck; Lieven Hollevoet; Praveen Raghavan; Liesbet Van der Perre; Francky Catthoor (SiPS, 2008)

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor. - Andy Lambrechts; Praveen Raghavan; Murali Jayapala; Francky Catthoor; Diederik Verkest (VLSI Design, 2008)

Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling. - Yuki Kobayashi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. - David Atienza; Praveen Raghavan; José Luis Ayala; Giovanni De Micheli; Francky Catthoor; Diederik Verkest; Marisa López-Vallejo (Integr., 2008)

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2009)

SARA: StreAm register allocation. - Praveen Raghavan; Francky Catthoor (CODES+ISSS, 2009)

Compilation Technique for Loop Overhead Minimization. - Nikolas Kroupis; Praveen Raghavan; Murali Jayapala; Francky Catthoor; Dimitrios Soudris (DSD, 2009)

Parallelization exploration of wireless applications using MPA. - Martin Palkovic; Praveen Raghavan; Thomas J. Ashby; Andy Folens; Hans Cappelle; Miguel Glassee; Liesbet Van der Perre; Francky Catthoor (PARCO, 2009)

Novel energy-efficient scalable soft-output SSFE MIMO detector architectures. - Robert Fasthuber; Min Li 001; David Novo; Praveen Raghavan; Liesbet Van der Perre; Francky Catthoor (ICSAMOS, 2009)

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. - David Novo; Robert Fasthuber; Praveen Raghavan; André Bourdoux; Min Li 001; Liesbet Van der Perre; Francky Catthoor (SiPS, 2009)

Register file exploration for a multi-standard wireless forward error correction ASIP. - Praveen Raghavan; Francky Catthoor (SiPS, 2009)

Locality optimization in a compiler for wireless applications. - Javed Absar; Praveen Raghavan; Andy Lambrechts; Min Li 001; Murali Jayapala; Francky Catthoor (Des. Autom. Embed. Syst., 2009)

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors. - Ittetsu Taniguchi; Praveen Raghavan; Murali Jayapala; Francky Catthoor; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

EMPIRE: Empirical power/area/timing models for register files. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (Microprocess. Microsystems, 2009)

Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures. - Praveen Raghavan; Andy Lambrechts; Murali Jayapala; Francky Catthoor; Diederik Verkest (IEEE Trans. Computers, 2009)

Playing the trade-off game: Architecture exploration using Coffeee. - Praveen Raghavan; Murali Jayapala; Andy Lambrechts; Javed Absar; Francky Catthoor (ACM Trans. Design Autom. Electr. Syst., 2009)

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. - Andy Lambrechts; Praveen Raghavan; Murali Jayapala; Bingfeng Mei; Francky Catthoor; Diederik Verkest (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Coarse-Grained Reconfigurable Array Architectures. - Bjorn De Sutter; Praveen Raghavan; Andy Lambrechts (Handbook of Signal Processing Systems, 2010)

Compilation techniques for CGRAs: exploring all parallelization approaches. - Tom Vander Aa; Praveen Raghavan; Scott A. Mahlke; Bjorn De Sutter; Aviral Shrivastava; Frank Hannig (CODES+ISSS, 2010)

Architectures for cognitive radio testbeds and demonstrators - An overview. - Oscar Gustafsson; Kiarash Amiri; Dennis Andersson; Anton Blad; Christian Bonnet; Joseph R. Cavallaro; Jeroen Declerck; Antoine Dejonghe; Patrik Eliardsson; Miguel Glassee; Aawatif Hayar; Lieven Hollevoet; et al. (CrownCom, 2010)

Exploiting finite precision information to guide data-flow mapping. - David Novo; Min Li 001; Robert Fasthuber; Praveen Raghavan; Francky Catthoor (DAC, 2010)

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI (Selected papers), 2010)

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Andrea Di Biagio; Ettore Speziale; Michele Tartara; et al. (ISVLSI, 2010)

SDR platform for 802.11n and 3-GPP LTE. - Jeroen Declerck; Praveen Raghavan; Frederik Naessens; Tom Vander Aa; Lieven Hollevoet; Antoine Dejonghe; Liesbet Van der Perre (ICSAMOS, 2010)

Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance. - David Novo; Angeliki Kritikakou; Praveen Raghavan; Liesbet Van der Perre; Jos Huisken; Francky Catthoor (SASP, 2010)

Future Software-Defined Radio Platforms and Mapping Flows. - Martin Palkovic; Praveen Raghavan; Min Li 001; Antoine Dejonghe; Liesbet Van der Perre; Francky Catthoor (IEEE Signal Process. Mag., 2010)

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors. - Bjorn De Sutter; Osman Allam; Praveen Raghavan; Roeland Vandebriel; Hans Cappelle; Tom Vander Aa; Bingfeng Mei (J. Signal Process. Syst., 2010)

An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. - Ittetsu Taniguchi; Mitsuya Uchida; Hiroyuki Tomiyama; Masahiro Fukui; Praveen Raghavan; Francky Catthoor (DSD, 2011)

Dart - a high level software-defined radio platform model for developing the run-time controller. - Martin Palkovic; Jeroen Declerck; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (ICASSP, 2011)

Automated architecture exploration for low energy reconfigurable AGU. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ISOCC, 2011)

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Ettore Speziale; Diego Melpignano; J. M. Zins; et al. (ReCoSoC, 2011)

A multi-threaded coarse-grained array processor for wireless baseband. - Tom Vander Aa; Martin Palkovic; Matthias Hartmann; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (SASP, 2011)

High level analysis of trade-offs across different partitioning schemes for wireless applications. - Prashant Agrawal; Robert Fasthuber; Praveen Raghavan; Tom Vander Aa; Ubaid Ahmad; Liesbet Van der Perre; Francky Catthoor (SiPS, 2011)

Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios. - Nikolaos Zompakis; Antonis Papanikolaou; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor (SiPS, 2011)

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors. - Robert Fasthuber; Min Li 001; David Novo; Praveen Raghavan; Liesbet Van der Perre; Francky Catthoor (J. Signal Process. Syst., 2011)

BTI impact on logical gates in nano-scale CMOS technology. - Seyab Khan; Said Hamdioui; Halil Kukner; Praveen Raghavan; Francky Catthoor (DDECS, 2012)

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis. - Seyab Khan; Said Hamdioui; Halil Kukner; Praveen Raghavan; Francky Catthoor (DFT, 2012)

Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms. - Prashant Agrawal; Kanishk Sugand; Martin Palkovic; Praveen Raghavan; Liesbet Van der Perre; Francky Catthoor (DSD, 2012)

Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model. - Halil Kukner; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (DSD, 2012)

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach. - Cristina Silvano; William Fornaciari; Stefano Crespi-Reghizzi; Giovanni Agosta; Gianluca Palermo; Vittorio Zaccaria; Patrick Bellasi; Fabrizio Castro; Simone Corbetta; Ettore Speziale; Diego Melpignano; J. M. Zins; et al. (INA-OCMC@HiPEAC, 2012)

A flexible platform architecture for Gbps wireless communication. - Jeroen Declerck; Prabhat Avasare; Miguel Glassee; Amir Amin; Erik Umans; Andy Dewilde; Praveen Raghavan; Martin Palkovic (ISSoC, 2012)

Algorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards. - Kiyotaka Kobayashi; Hidekuni Yomo; Min Li 001; Raf Appeltans; Hans Cappelle; Amir Amin; Aïssa Couvreur; Matthias Hartmann; André Bourdoux; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (VTC Spring, 2012)

DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller. - Martin Palkovic; Jeroen Declerck; Prabhat Avasare; Miguel Glassee; Andy Dewilde; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (J. Signal Process. Syst., 2012)

CMOS low-power transceivers for 60GHz multi Gbit/s communications. - Vojkan Vidojkovic; Viki Szortyka; Khaled Khalaf; Giovanni Mangraviti; Bertrand Parvais; Kristof Vaesen; Steven Brebels; Annachiara Spagnolo; Michael Libois; John R. Long; Kuba Raczkowski; Praveen Raghavan; et al. (CICC, 2013)

Early exploration for platform architecture instantiation with multi-mode application partitioning. - Prashant Agrawal; Praveen Raghavan; Matthias Hartmann; Namita Sharma 001; Liesbet Van der Perre; Francky Catthoor (DAC, 2013)

Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design. - Matthias Hartmann; Praveen Raghavan; Liesbet Van der Perre; Prashant Agrawal; Wim Dehaene (DSD, 2013)

Bias temperature instability analysis in SRAM decoder. - Seyab Khan; Said Hamdioui; Halil Kukner; Praveen Raghavan; Francky Catthoor (ETS, 2013)

A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited). - Min Li 001; Amir Amin; Raf Appeltans; Andy Folens; Ubaid Ahmad; Hans Cappelle; Peter Debacker; Lieven Hollevoet; André Bourdoux; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (GlobalSIP, 2013)

A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication. - Meng Li 012; Frederik Naessens; Min Li 001; Peter Debacker; Claude Desset; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (GlobalSIP, 2013)

Data memory optimization in LTE downlink. - Namita Sharma 001; Tom Vander Aa; Prashant Agrawal; Praveen Raghavan; Preeti Ranjan Panda; Francky Catthoor (ICASSP, 2013)

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity. - Seyab Khan; Mottaqiallah Taouil; Said Hamdioui; Halil Kukner; Praveen Raghavan; Francky Catthoor (IDT, 2013)

An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard. - Meng Li 012; Frederik Naessens; Peter Debacker; Praveen Raghavan; Claude Desset; Min Li 001; Antoine Dejonghe; Liesbet Van der Perre (SiPS, 2013)

Energy impact in the design space exploration of loop buffer schemes in embedded systems. - Antonio Artés; José Luis Ayala; Robert Fasthuber; Praveen Raghavan; Francky Catthoor (VLSI-SoC, 2013)

Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication. - Prabhat Avasare; Jeroen Declerck; Miguel Glassee; Amir Amin; Erik Umans; Praveen Raghavan; Martin Palkovic (Int. J. Embed. Real Time Commun. Syst., 2013)

Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios. - Nikolaos Zompakis; Antonis Papanikolaou; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor (Int. J. Wirel. Inf. Networks, 2013)

Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model. - Halil Kükner; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (Microprocess. Microsystems, 2013)

Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems. - Antonio Artés; Robert Fasthuber; José Luis Ayala; Praveen Raghavan; Francky Catthoor (J. Signal Process. Syst., 2013)

Coarse-Grained Reconfigurable Array Architectures. - Bjorn De Sutter; Praveen Raghavan; Andy Lambrechts (Handbook of Signal Processing Systems, 2013)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Resolving the memory bottleneck for single supply near-threshold computing. - Tobias Gemmeke; Mohamed M. Sabry; Jan Stuijt; Praveen Raghavan; Francky Catthoor; David Atienza (DATE, 2014)

Bias Temperature Instability analysis of FinFET based SRAM cells. - Seyab Khan; Innocent Agbo; Said Hamdioui; Halil Kukner; Ben Kaczer; Praveen Raghavan; Francky Catthoor (DATE, 2014)

Feasibility exploration of NVM based I-cache through MSHR enhancements. - Manu Komalan; José Ignacio Gómez Pérez; Christian Tenllado; Praveen Raghavan; Matthias Hartmann; Francky Catthoor (DATE, 2014)

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. - Halil Kukner; Pieter Weckx; Sebastien Morrison; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (DSD, 2014)

Majority Logic Synthesis for Spin Wave Technology. - Odysseas Zografos; Luca Gaetano Amarù; Pierre-Emmanuel Gaillardon; Praveen Raghavan; Giovanni De Micheli (DSD, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories. - Matthias Hartmann; Halil Kükner; Prashant Agrawal; Praveen Raghavan; Liesbet Van der Perre; Wim Dehaene (ACM Great Lakes Symposium on VLSI, 2014)

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology. - Halil Kukner; Moustafa A. Khatib; Sebastien Morrison; Pieter Weckx; Praveen Raghavan; Ben Kaczer; Francky Catthoor; Liesbet Van der Perre; Rudy Lauwereins; Guido Groeseneken (ISQED, 2014)

System-level assessment and area evaluation of Spin Wave logic circuits. - Odysseas Zografos; Praveen Raghavan; Luca Gaetano Amarù; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Diederik Verkest; Aaron Thean (NANOARCH, 2014)

Hard versus Soft Software Defined Radio. - Wim Meeus; Tom Vander Aa; Praveen Raghavan; Dirk Stroobandt (VLSID, 2014)

System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform. - Prashant Agrawal; Dragomir Milojevic; Praveen Raghavan; Francky Catthoor; Liesbet Van der Perre; Eric Beyne; Ravi Varadarajan (IEEE Embed. Syst. Lett., 2014)

Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path. - Ittetsu Taniguchi; Kohei Aoki; Hiroyuki Tomiyama; Praveen Raghavan; Francky Catthoor; Masahiro Fukui (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Characterization and simulation methodology for time-dependent variability in advanced technologies. - Pieter Weckx; Ben Kaczer; Praveen Raghavan; Jacopo Franco; Marko Simicic; Philippe J. Roussel; Dimitri Linten; Aaron Thean; Diederik Verkest; Francky Catthoor; Guido Groeseneken (CICC, 2015)

Impact of interconnect multiple-patterning variability on SRAMs. - Ioannis Karageorgos; Michele Stucchi; Praveen Raghavan; Julien Ryckaert; Zsolt Tokei; Diederik Verkest; Rogier Baert; Sushil Sakhare; Wim Dehaene (DATE, 2015)

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Stefan Cosemans; Pieter Weckx; Praveen Raghavan; Francky Catthoor (DTIS, 2015)

The defect-centric perspective of device and circuit reliability - From individual defects to circuits. - Ben Kaczer; Jacopo Franco; Pieter Weckx; Philippe Roussel; Erik Bury; Moonju Cho; Robin Degraeve; Dimitri Linten; Guido Groeseneken; Halil Kukner; Praveen Raghavan; Francky Catthoor; et al. (ESSDERC, 2015)

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling. - Marie Garcia Bardon; P. Schuddinck; Praveen Raghavan; Doyoung Jang; Dmitry Yakimets; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Impact of device and interconnect process variability on clock distribution. - Nathalie Fievet; Praveen Raghavan; Rogier Baert; Frédéric Robert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Modeling FinFET metal gate stack resistance for 14nm node and beyond. - Kenichi Miyaguchi; Bertrand Parvais; Lars-Åke Ragnarsson; Piet Wambacq; Praveen Raghavan; Abdelkarim Mercha; Anda Mocuta; Diederik Verkest; Aaron Thean (ICICDT, 2015)

Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

Area and routing efficiency of SWD circuits compared to advanced CMOS. - Odysseas Zografos; Praveen Raghavan; Yasser Sherazi; Adrien Vaysset; Florin Ciubotaru; Bart Soree; Rudy Lauwereins; Iuliana P. Radu; Aaron Thean (ICICDT, 2015)

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. - Chenyun Pan; Praveen Raghavan; Francky Catthoor; Zsolt Tokei; Azad Naeemi (ISQED, 2015)

Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power. - Behzad Zeinali; Jens Kargaard Madsen; Praveen Raghavan; Farshad Moradi (ISVLSI, 2015)

STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance. - Raf Appeltans; Stefan Cosemans; Praveen Raghavan; Diederik Verkest; Liesbet Van der Perre; Wim Dehaene (NVMSA, 2015)

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Halil Kukner; Pieter Weckx; Praveen Raghavan; Francky Catthoor (VTS, 2015)

Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. - Halil Kükner; Pieter Weckx; Sébastien Morrison; Jacopo Franco; Maria Toledano-Luque; Moonju Cho; Praveen Raghavan; Ben Kaczer; Doyoung Jang; Kenichi Miyaguchi; Marie Garcia Bardon; Francky Catthoor; et al. (Microprocess. Microsystems, 2015)

Array Interleaving - An Energy-Efficient Data Layout Transformation. - Namita Sharma 001; Preeti Ranjan Panda; Francky Catthoor; Praveen Raghavan; Tom Vander Aa (ACM Trans. Design Autom. Electr. Syst., 2015)

A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency. - Robert Fasthuber; Praveen Raghavan; Liesbet Van der Perre; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Memories for NTC. - Tobias Gemmeke; Mohamed M. Sabry; Jan Stuijt; Pieter Schuddinck; Praveen Raghavan; Francky Catthoor (Near Threshold Computing, 2016)

Comparative BTI analysis for various sense amplifier designs. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Praveen Raghavan; Francky Catthoor (DDECS, 2016)

Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective. - Tarun Agarwal; Iuliana P. Radu; Praveen Raghavan; Gianluca Fiori; Aaron Thean; Marc M. Heyns; Wim Dehaene (ESSCIRC, 2016)

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs. - Ravi Patel 001; Kan Xu; Eby G. Friedman; Praveen Raghavan (ACM Great Lakes Symposium on VLSI, 2016)

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. - Dimitrios Stamoulis; Simone Corbetta; Dimitrios Rodopoulos; Pieter Weckx; Peter Debacker; Brett H. Meyer; Ben Kaczer; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2016)

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Sung Kyu Lim (ICCAD, 2016)

Power noise in 14, 10, and 7 nm FinFET CMOS technologies. - Ravi Patel 001; Eby G. Friedman; Praveen Raghavan (ISCAS, 2016)

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Diederik Verkest; Aaron Thean; Sung Kyu Lim (ISLPED, 2016)

Device/system performance modeling of stacked lateral NWFET logic. - Victor Huang; Chenyun Pan; Dmitry Yakimets; Praveen Raghavan; Azad Naeemi (ISQED, 2016)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. - Innocent Agbo; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Stefan Cosemans; Praveen Raghavan; Francky Catthoor; Wim Dehaene (ISVLSI, 2016)

Inversion optimization in Majority-Inverter Graphs. - Eleonora Testa; Mathias Soeken; Odysseas Zografos; Luca Gaetano Amarù; Praveen Raghavan; Rudy Lauwereins; Pierre-Emmanuel Gaillardon; Giovanni De Micheli (NANOARCH, 2016)

Non-volatile spin wave majority gate at the nanoscale. - Odysseas Zografos; Sourav Dutta; Mauricio Manfrini; Adrien Vaysset; Bart Sorée; Azad Naeemi; Praveen Raghavan; Rudy Lauwereins; Iuliana P. Radu (CoRR, 2016)

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (DAC, 2017)

Wave pipelining for majority-based beyond-CMOS technologies. - Odysseas Zografos; A. De Meester; Eleonora Testa; Mathias Soeken; Pierre-Emmanuel Gaillardon; Giovanni De Micheli; Luca Gaetano Amarù; Praveen Raghavan; Francky Catthoor; Rudy Lauwereins (DATE, 2017)

Material selection and device design guidelines for two-dimensional materials based TFETs. - Tarun Agarwal; Bart Soree; Iuliana P. Radu; Praveen Raghavan; Gianluca Fiori; Marc M. Heyns; Wim Dehaene (ESSDERC, 2017)

Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Dmitry Yakimets; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ESSDERC, 2017)

IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. - Luca Mattii; Dragomir Milojevic; Peter Debacker; Yasser Sherazi; Mladen Berekovic; Praveen Raghavan (ICCAD, 2017)

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. - Yibo Lin; Peter Debacker; Darko Trivkovic; Ryoung-Han Kim; Praveen Raghavan; David Z. Pan (ICCD, 2017)

Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching. - Behzad Zeinali; Jens Kargaard Madsen; Praveen Raghavan; Farshad Moradi (ICCD, 2017)

Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. - Mohit Kumar Gupta 001; Pieter Weckx; Stefan Cosemans; Pieter Schuddinck; Rogier Baert; Doyoung Jang; Yasser Sherazi; Praveen Raghavan; Alessio Spessot; Anda Mocuta; Wim Dehaene (ICICDT, 2017)

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology. - Behzad Zeinali; Jens Kargaard Madsen; Praveen Raghavan; Farshad Moradi (Int. J. Circuit Theory Appl., 2017)

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier. - Innocent Agbo; Mottaqiallah Taouil; Daniel Kraak; Said Hamdioui; Halil Kukner; Pieter Weckx; Praveen Raghavan; Francky Catthoor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. - Raf Appeltans; Praveen Raghavan; Gouri Sankar Kar; Arnaud Furnémont; Liesbet Van der Perre; Wim Dehaene (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs. - Kan Xu; Ravi Patel 001; Praveen Raghavan; Eby G. Friedman (Integr., 2018)

A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs. - Behzad Zeinali; Jens Kargaard Madsen; Praveen Raghavan; Farshad Moradi (IEEE Trans. Emerg. Top. Comput., 2019)