A Power and Performance Model for Network-on-Chip Architectures. - Nilanjan Banerjee; Praveen Vellanki; Karam S. Chatha (DATE, 2004)

Quality-of-service and error control techniques for network-on-chip architectures. - Praveen Vellanki; Nilanjan Banerjee; Karam S. Chatha (ACM Great Lakes Symposium on VLSI, 2004)

Quality-of-service and error control techniques for mesh-based network-on-chip architectures. - Praveen Vellanki; Nilanjan Banerjee; Karam S. Chatha (Integr., 2005)