ATE test time reduction using asynchronous clock period. - Praveen Venkataramani; Vishwani D. Agrawal (ITC, 2013)

Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. - Praveen Venkataramani; Vishwani D. Agrawal (VLSI Design, 2013)

Finding best voltage and frequency to shorten power-constrained test time. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (VTS, 2013)

A Test Time Theorem and its Applications. - Praveen Venkataramani; Suraj Sindia; Vishwani D. Agrawal (J. Electron. Test., 2014)