A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. - Vijay Khawshe; Kapil Vyas; Renu Rangnekar; Prateek Goyal; Vijay Krishna; Kashinath Prabhu; Pravin Kumar Venkatesan; Leneesh Raghavan; Rajkumar Palwai; M. Thrivikraman; Kunal Desai; Abhijit Abhyankar (VLSI Design, 2009)

A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI. - Wayne D. Dettloff; John C. Eble; Lei Luo 006; Pravin Kumar Venkatesan; Fred Heaton; Teva Stone; Barry Daly (ISSCC, 2010)

High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. - Kunal Desai; Rajasekhar Nagulapalli; Vijay Krishna; Rajkumar Palwai; Pravin Kumar Venkatesan; Vijay Khawshe (VLSI Design, 2010)

A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems. - Kambiz Kaviani; Michael Bucher; Bruce Su; Barry Daly; Bill Stonecypher; Wayne D. Dettloff; Teva Stone; Kashinath Prabhu; Pravin Kumar Venkatesan; Fred Heaton; Ravi T. Kollipara; Yi Lu; et al. (ISSCC, 2013)

A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. - Michael Bucher; Ravi T. Kollipara; Bruce Su; Liji Gopalakrishnan; Kashinath Prabhu; Pravin Kumar Venkatesan; Kambiz Kaviani; Barry Daly; William F. Stonecypher; Wayne D. Dettloff; Teva Stone; Fred Heaton; et al. (IEEE J. Solid State Circuits, 2014)