A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique. - Jialin Zhao 001; Yunzhi Dong; Wenhua Yang 002; Hajime Shibata; Prawal Shrestha; Zhao Li; Trevor C. Caldwell; José B. Silva; Jeffrey C. Gealow (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. - Hajime Shibata; Gerry Taylor; Bob Schell; Victor Kozlov; Sharvil Patil; Donald Paterson; Asha Ganesan; Yunzhi Dong; Wenhua Yang 002; Yue Yin; Zhao Li; Prawal Shrestha; et al. (ISSCC, 2020)

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. - Sharvil Patil; Asha Ganesan; Hajime Shibata; Victor Kozlov; Gerry Taylor; Qingnan Yu; Zhao Li; Zeynep Lulec; Konstantinos Vasilakopoulos; Prawal Shrestha; Donald Paterson; Raviteja Theertham; et al. (ISSCC, 2024)

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. - Rishabh Mittal; Hajime Shibata; Sharvil Patil; Erik Krommenhoek; Prawal Shrestha; Gabriele Manganaro; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2024)

A -90-dBFS-IM3, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors. - Sharvil Patil; Asha Ganesan; Hajime Shibata; Victor Kozlov; Gerry Taylor; Prawal Shrestha; Zhao Li; Sevil Zeynep Lulec; Konstantinos Vasilakopoulos; Raviteja Theertham; Donald Paterson; Qingnan Yu; et al. (IEEE J. Solid State Circuits, 2024)