A new statistical setup and hold time definition. - Xiaoliang Bai; Prayag Patel; Xiaonan Zhang (ICICDT, 2012)

Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology. - Animesh Datta; Mohamed H. Abu-Rahma; Sachin Dileep Dasnurkar; Hadi Rasouli; Sean Tamjidi; Ming Cai; Samit Sengupta; P. R. Chidambaram; Raghavan Thirumala; Nikhil Kulkarni; Prasanna Seeram; Prasad Bhadri; et al. (ISQED, 2013)

Experiments and analysis to characterize logic state retention limitations in 28nm process node. - Sachin Dileep Dasnurkar; Animesh Datta; Mohamed H. Abu-Rahma; Hieu Nguyen; Martin Villafana; Hadi Rasouli; Sean Tamjidi; Ming Cai; Samit Sengupta; P. R. Chidambaram; Raghavan Thirumala; Nikhil Kulkarni; et al. (VTS, 2013)