Low Power Sorters Using Clock Gating. - Preethi; Mohan Govindsa Kabadi; K. Sudeendra Kumar; K. K. Mahapatra (iSES, 2021)

Implementation of Elliptic Curve Cryptosystem with Bitcoin Curves on SECP256k1, NIST256p, NIST521p, and LLL. - Mohammed Mujeer Ulla; Preethi; Md. Sameeruddin Khan; Deepak S. Sakkari (J. ICT Stand., 2023)

Sorter Design with Structured Low Power Techniques. - Preethi; Mohan Govindsa Kabadi; Sudeendra Kumar K; K. K. Mahapatra (SN Comput. Sci., 2023)

FPGA-based dual-layer authentication scheme utilizing AES and ECC for unmanned aerial vehicles. - Kumar Sekhar Roy; Murikipudi Sujith; Bandi Bhanu; Preethi; Ruhul Amin Hazarika (EURASIP J. Wirel. Commun. Netw., 2024)

Optimizing Polynomial and Regularization Techniques for Enhanced Housing Price Prediction Accuracy. - Preethi; D. H. R. Murthy; Vani A. Hiremani; Raghavendra M. Devadas; R. Sapna (SN Comput. Sci., 2025)