A Flexible Scheme for State Assignment Based on Characteristics of the FSM. - Biswadip Mitra; Preeti Ranjan Panda; Parimal Pal Chaudhuri (ICCAD, 1991)

Estimating the Complexity of Synthesized Designs from FSM Specifications. - Biswadip Mitra; Preeti Ranjan Panda; Parimal Pal Chaudhuri (IEEE Des. Test Comput., 1993)

1995 high level synthesis design repository. - Preeti Ranjan Panda; Nikil D. Dutt (ISSS, 1995)

Reducing Address Bus Transitions for Low Power Memory Mapping. - Preeti Ranjan Panda; Nikil D. Dutt (ED&TC, 1996)

Low-power mapping of behavioral arrays to multiple memories. - Preeti Ranjan Panda; Nikil D. Dutt (ISLPED, 1996)

Memory Organization for Improved Data Cache Performance in Embedded Processors. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ISSS, 1996)

Efficient utilization of scratch-pad memory in embedded processor applications. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ED&TC, 1997)

Exploiting off-chip memory access modes in high-level synthesis. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ICCAD, 1997)

A Data Alignment Technique for Improving Cache Performance. - Preeti Ranjan Panda; Hiroshi Nakamura; Nikil D. Dutt; Alexandru Nicolau (ICCD, 1997)

Improving cache Performance Through Tiling and Data Alignment. - Preeti Ranjan Panda; Hiroshi Nakamura; Nikil D. Dutt; Alexandru Nicolau (IRREGULAR, 1997)

Architectural Exploration and Optimization of Local Memory in Embedded Systems. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ISSS, 1997)

Behavioral Array Mapping into Multiport Memories Targeting Low Power. - Preeti Ranjan Panda; Nikil D. Dutt (VLSI Design, 1997)

Memory data organization for improved cache performance in embedded processor applications. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ACM Trans. Design Autom. Electr. Syst., 1997)

Data Cache Sizing for Embedded Processor Applications. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (DATE, 1998)

Incorporating DRAM access modes into high-level synthesis. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Memory bank customization and assignment in behavioral synthesis. - Preeti Ranjan Panda (ICCAD, 1999)

Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. - Preeti Ranjan Panda; Hiroshi Nakamura; Nikil D. Dutt; Alexandru Nicolau (IEEE Trans. Computers, 1999)

Local memory exploration and optimization in embedded systems. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Low-power memory mapping through reducing address bus activity. - Preeti Ranjan Panda; Nikil D. Dutt (IEEE Trans. Very Large Scale Integr. Syst., 1999)

On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau (ACM Trans. Design Autom. Electr. Syst., 2000)

SystemC: A Modeling Platform Supporting Multiple Design Abstractions. - Preeti Ranjan Panda (ISSS, 2001)

Cache-efficient memory layout of aggregate data structures. - Preeti Ranjan Panda; Luc Séméria; Giovanni De Micheli (ISSS, 2001)

New Design Paradigms: What Needs to be Standardized?. - Wolfgang Rosenstiel; Brian Bailey; Masahiro Fujita; Guang R. Gao; Rajesh K. Gupta 001; Preeti Ranjan Panda (ISSS, 2001)

Embedded Memories in System Design: Technology, Application, Design and Tools. - Doris Keitel-Schulz; Norbert Wehn; Francky Catthoor; Preeti Ranjan Panda (VLSI Design, 2001)

Data Memory Organization and Optimizations in Application-Specific Systems. - Preeti Ranjan Panda; Nikil D. Dutt; Alexandru Nicolau; Francky Catthoor; Arnout Vandecappelle; Erik Brockmeyer; Chidamber Kulkarni; Eddy de Greef (IEEE Des. Test Comput., 2001)

Data and memory optimization techniques for embedded systems. - Preeti Ranjan Panda; Francky Catthoor; Nikil D. Dutt; Koen Danckaert; Erik Brockmeyer; Chidamber Kulkarni; Arnout Vandecappelle; Per Gunnar Kjeldsberg (ACM Trans. Design Autom. Electr. Syst., 2001)

An integrated algorithm for memory allocation and assignment in high-level synthesis. - Jaewon Seo; Taewhan Kim; Preeti Ranjan Panda (DAC, 2002)

Memory Architectures for Embedded Systems-On-Chip. - Preeti Ranjan Panda; Nikil D. Dutt (HiPC, 2002)

An energy-conscious algorithm for memory port allocation. - Preeti Ranjan Panda; Lakshmikantam Chitturi (ICCAD, 2002)

Specification and Design of Multi-Million Gate SOCs. - Ramesh Chandra; Preeti Ranjan Panda; Jörg Henkel; Sri Parameswaran; Loganath Ramachandran (VLSI Design, 2003)

Memory allocation and mapping in high-level synthesis - an integrated approach. - Jaewon Seo; Taewhan Kim; Preeti Ranjan Panda (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Extracting Exact Finite State Machines from Behavioral SystemC Descriptions. - Vikram Singh Saun; Preeti Ranjan Panda (VLSI Design, 2005)

Abridged addressing: a low power memory addressing strategy. - Preeti Ranjan Panda (ASP-DAC, 2006)

Rapid estimation of control delay from high-level specifications. - Gagan Raj Gupta 001; Madhur Gupta; Preeti Ranjan Panda (DAC, 2006)

The impact of loop unrolling on controller delay in high level synthesis. - Srikanth Kurra; Neeraj Kumar Singh 004; Preeti Ranjan Panda (DATE, 2007)

An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet Transform. - Rahul Jain 004; Preeti Ranjan Panda (ISCAS, 2007)

Power Reduction in VLIW Processor with Compiler Driven Bypass Network. - Neeraj Goel; Anshul Kumar; Preeti Ranjan Panda (VLSI Design, 2007)

Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform. - Rahul Jain 004; Preeti Ranjan Panda (VLSI Design, 2007)

Customization of Register File Banking Architecture for Low Power. - Rakesh Nalluri; Rohan Garg 003; Preeti Ranjan Panda (VLSI Design, 2007)

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. - Anup Gangwar; M. Balakrishnan; Preeti Ranjan Panda; Anshul Kumar (Int. J. Parallel Program., 2007)

REWIRED - Register Write Inhibition by Resource Dedication. - Pushkar Tripathi; Rohan Jain; Srikanth Kurra; Preeti Ranjan Panda (ASP-DAC, 2008)

Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors. - B. V. N. Silpa; Anjul Patney; Tushar Krishna; Preeti Ranjan Panda; G. S. Visweswaran (ICCAD, 2008)

Guest Editor Introduction: Special Issue on Multiprocessor-based Embedded Systems. - Preeti Ranjan Panda (Int. J. Parallel Program., 2008)

Online cache state dumping for processor debug. - Anant Vishnoi; Preeti Ranjan Panda; M. Balakrishnan (DAC, 2009)

A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. - Aryabartta Sahu; M. Balakrishnan; Preeti Ranjan Panda (DATE, 2009)

Cache aware compression for processor debug support. - Anant Vishnoi; Preeti Ranjan Panda; M. Balakrishnan (DATE, 2009)

Adaptive Partitioning of Vertex Shader for Low Power High Performance Geometry Engine. - B. V. N. Silpa; Kumar S. S. Vemuri; Preeti Ranjan Panda (ISVC (1), 2009)

A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009. - Rajendran Panda; Preeti Ranjan Panda (J. Low Power Electron., 2009)

FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. - Gummidipudi Krishnaiah; B. V. N. Silpa; Preeti Ranjan Panda; Anshul Kumar (CODES+ISSS, 2010)

Rank based dynamic voltage and frequency scaling fortiled graphics processors. - B. V. N. Silpa; Gummidipudi Krishnaiah; Preeti Ranjan Panda (CODES+ISSS, 2010)

Enhancing post-silicon processor debug with Incremental Cache state Dumping. - Preeti Ranjan Panda; Anant Vishnoi; M. Balakrishnan (VLSI-SoC, 2010)

Front-End Design Flows for Systems on Chip: An Embedded Tutorial. - Anshul Kumar; Preeti Ranjan Panda (VLSI Design, 2010)

Guest Editorial: Special Issue on VLSI Design and Embedded Systems. - Preeti Ranjan Panda; Rajendran Panda (Int. J. Parallel Program., 2010)

Exploiting temporal decoupling to accelerate trace-driven NoC emulation. - Gummidipudi Krishnaiah; B. V. N. Silpa; Preeti Ranjan Panda; Anshul Kumar (CODES+ISSS, 2011)

A SysML Profile for Development and Early Validation of TLM 2.0 Models. - Vaibhav Jain; Anshul Kumar; Preeti Ranjan Panda (ECMFA, 2011)

A UML based framework for efficient validation of TLM 2 models. - Vaibhav Jain; Anshul Kumar; Preeti Ranjan Panda (FDL, 2011)

Compressing Cache State for Postsilicon Processor Debug. - Preeti Ranjan Panda; M. Balakrishnan; Anant Vishnoi (IEEE Trans. Computers, 2011)

Integrating software caches with scratch pad memory. - Prasenjit Chakraborty; Preeti Ranjan Panda (CASES, 2012)

Efficient on-line algorithm for maintaining k-cover of sparse bit-strings. - Amit Kumar 001; Preeti Ranjan Panda; Smruti R. Sarangi (FSTTCS, 2012)

Exploiting UML based validation for compliance checking of TLM 2 based models. - Vaibhav Jain; Anshul Kumar; Preeti Ranjan Panda (Des. Autom. Embed. Syst., 2012)

SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems. - Prasenjit Chakraborty; Preeti Ranjan Panda (CASES, 2013)

Message from the program co-chairs. - Radu Marculescu; Preeti Ranjan Panda (CODES+ISSS, 2013)

Space sensitive cache dumping for post-silicon validation. - Sandeep Chandran; Smruti R. Sarangi; Preeti Ranjan Panda (DATE, 2013)

Data memory optimization in LTE downlink. - Namita Sharma 001; Tom Vander Aa; Prashant Agrawal; Praveen Raghavan; Preeti Ranjan Panda; Francky Catthoor (ICASSP, 2013)

Power Supply Efficiency Aware Server Allocation in Data Centers. - Preeti Ranjan Panda; Manoj Jain; Anubha Verma; Dipankar Sarma; Vaidyanathan Srinivasan (VLSI Design, 2013)

Array scalarization in high level synthesis. - Preeti Ranjan Panda; Namita Sharma 001; Arun Kumar Pilania; Gummidipudi Krishnaiah; Sreenivas Subramoney; Ashok Jagannathan (ASP-DAC, 2014)

Energy optimization in Android applications through wakelock placement. - Faisal Alam; Preeti Ranjan Panda; Nikhil Tripathi; Namita Sharma 001; Sanjiv Narayan (DATE, 2014)

Energy efficient data flow transformation for Givens Rotation based QR Decomposition. - Namita Sharma 001; Preeti Ranjan Panda; Min Li 001; Prashant Agrawal; Francky Catthoor (DATE, 2014)

High level energy modeling of controller logic in data caches. - Preeti Ranjan Panda; Sourav Roy; Srikanth Chandrasekaran; Namita Sharma 001; Jasleen Kaur; Sarath Kumar Kandalam; Nagaraj N. (ACM Great Lakes Symposium on VLSI, 2014)

Shared-port register file architecture for low-energy VLIW processors. - Neeraj Goel; Anshul Kumar; Preeti Ranjan Panda (ACM Trans. Archit. Code Optim., 2014)

Energy efficient FFT implementation through stage skipping and merging. - Namita Sharma 001; Preeti Ranjan Panda; Francky Catthoor (CODES+ISSS, 2015)

Power Optimization Techniques for DDR3 SDRAM. - Preeti Ranjan Panda; Vishal Patel; Praxal Shah; Namita Sharma 001; Vaidyanathan Srinivasan; Dipankar Sarma (VLSID, 2015)

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects. - Sandeep Chandran; Eldhose Peter; Preeti Ranjan Panda; Smruti R. Sarangi (CoRR, 2015)

Array Interleaving - An Energy-Efficient Data Layout Transformation. - Namita Sharma 001; Preeti Ranjan Panda; Francky Catthoor; Praveen Raghavan; Tom Vander Aa (ACM Trans. Design Autom. Electr. Syst., 2015)

Extending trace history through tapered summaries in post-silicon validation. - Sandeep Chandran; Preeti Ranjan Panda; Deepak Chauhan; Sharad Kumar; Smruti R. Sarangi (ASP-DAC, 2016)

Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (DATE, 2016)

A Generic Implementation of Barriers Using Optical Interconnects. - Sandeep Chandran; Eldhose Peter; Preeti Ranjan Panda; Smruti R. Sarangi (VLSID, 2016)

Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD. - Namita Sharma 001; Preeti Ranjan Panda; Francky Catthoor; Min Li 001; Prashant Agrawal (ACM Trans. Embed. Comput. Syst., 2016)

Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures. - Iason Filippopoulos; Namita Sharma 001; Francky Catthoor; Per Gunnar Kjeldsberg; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2016)

Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures. - Prasenjit Chakraborty; Preeti Ranjan Panda; Sandeep Sen (ACM Trans. Design Autom. Electr. Syst., 2016)

Area-Aware Cache Update Trackers for Postsilicon Validation. - Sandeep Chandran; Smruti R. Sarangi; Preeti Ranjan Panda (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A coordinated multi-agent reinforcement learning approach to multi-level cache co-partitioning. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (DATE, 2017)

Reusing trace buffers to enhance cache performance. - Neetu Jindal; Preeti Ranjan Panda; Smruti R. Sarangi (DATE, 2017)

Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network. - Rahul Jain 004; Preeti Ranjan Panda; Sreenivas Subramoney (ACM Trans. Archit. Code Optim., 2017)

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. - Sandeep Chandran; Preeti Ranjan Panda; Smruti R. Sarangi; Ayan Bhattacharyya; Deepak Chauhan; Sharad Kumar (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Memory Architectures. - Preeti Ranjan Panda (Handbook of Hardware/Software Codesign, 2017)

Exploration of Loop Unroll Factors in High Level Synthesis. - Preeti Ranjan Panda; Namita Sharma 001; Srikanth Kurra; Khushboo Anil Bhartia; Neeraj Kumar Singh 004 (VLSID, 2018)

Reusing Trace Buffers as Victim Caches. - Neetu Jindal; Preeti Ranjan Panda; Smruti R. Sarangi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. - Neetu Jindal; Sandeep Chandran; Preeti Ranjan Panda; Sanjiva Prasad; Abhay Mitra; Kunal Singhal; Shubham Gupta; Shikhar Tuli (DAC, 2019)

FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories. - Lokesh Siddhu; Preeti Ranjan Panda (DATE, 2019)

Techniques for Debug of Low Power SoCs. - Sankaran M. Menon; Ashish Gupta; Chinna Prudvi; Rolf Kühnis; Sukhbinder Singh Takhar; Spencer K. Millican; Eric Rentschler; Pandy Kalimuthu; Preeti Ranjan Panda; Priyadarsan Patra (MTV, 2019)

Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN Applications. - Vivek Kamalkant Parmar; Swatilekha Majumdar; Preeti Ranjan Panda; Manan Suri (VLSID, 2019)

Alleria: An Advanced Memory Access Profiling Framework. - Hadi Brais; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2019)

PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor. - Lokesh Siddhu; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2019)

Editorial-December 2020. - Preeti Ranjan Panda (IEEE Embed. Syst. Lett., 2020)

Enhancing Network-on-Chip Performance by Reusing Trace Buffers. - Neetu Jindal; Shubhani Gupta; Divya Praneetha Ravipati; Preeti Ranjan Panda; Smruti R. Sarangi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

REAL: REquest Arbitration in Last Level Caches. - Sakshi Tiwari; Shreshth Tuli; Isaar Ahmad; Ayushi Agarwal; Preeti Ranjan Panda; Sreenivas Subramoney (ACM Trans. Embed. Comput. Syst., 2020)

A Survey of Cache Simulators. - Hadi Brais; Rajshekar Kalayappan; Preeti Ranjan Panda (ACM Comput. Surv., 2021)

Leakage-Aware Dynamic Thermal Management of 3D Memories. - Lokesh Siddhu; Rajesh Kedia; Preeti Ranjan Panda (ACM Trans. Design Autom. Electr. Syst., 2021)

CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance. - Lokesh Siddhu; Rajesh Kedia; Preeti Ranjan Panda (DATE, 2022)

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems. - Lokesh Siddhu; Rajesh Kedia; Shailja Pandey; Martin Rapp; Anuj Pathania; Jörg Henkel; Preeti Ranjan Panda (ACM Trans. Archit. Code Optim., 2022)

NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory. - Shailja Pandey; Preeti Ranjan Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies. - Divya Praneetha Ravipati; Rajesh Kedia; Victor M. van Santen; Jörg Henkel; Preeti Ranjan Panda; Hussam Amrouch (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Education Abstract: Thermal Challenges and Mitigation in 3D DRAM. - Preeti Ranjan Panda; Shailja Pandey (CODES+ISSS, 2023)

Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT. - Divya Praneetha Ravipati; Victor M. van Santen; Sami Salamin; Hussam Amrouch; Preeti Ranjan Panda (IEEE Trans. Very Large Scale Integr. Syst., 2023)

CABARRE: Request Response Arbitration for Shared Cache Management. - Garima Modi; Aritra Bagchi; Neetu Jindal; Ayan Mandal; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2023)

Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure. - Lokesh Siddhu; Aritra Bagchi; Rajesh Kedia; Isaar Ahmad; Shailja Pandey; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2023)

Editorial. - Preeti Ranjan Panda (IEEE Embed. Syst. Lett., 2023)

APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs. - Ayushi Agarwal; Radhika Dharwadkar; Isaar Ahmad; Krishna Kumar; P. J. Joseph; Sourav Roy; Prokash Ghosh; Preeti Ranjan Panda (VLSI-SoC, 2024)

POEM: Performance Optimization and Endurance Management for Non-volatile Caches. - Aritra Bagchi; Dharamjeet; Ohm Rishabh; Manan Suri; Preeti Ranjan Panda (ACM Trans. Design Autom. Electr. Syst., 2024)

COBRRA: COntention-aware cache Bypass with Request-Response Arbitration. - Aritra Bagchi; Dinesh Joshi; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2024)

NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching. - Shailja Pandey; Lokesh Siddhu; Preeti Ranjan Panda (ACM Trans. Design Autom. Electr. Syst., 2024)

3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints. - Shailja Pandey; Sayam Sethi; Preeti Ranjan Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy. - Aritra Bagchi; Ohm Rishabh; Preeti Ranjan Panda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance. - Shailja Pandey; Preeti Ranjan Panda (ACM Trans. Embed. Comput. Syst., 2024)

CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches. - Divya Praneetha Ravipati; Ramanuj Goel; Victor M. van Santen; Hussam Amrouch; Preeti Ranjan Panda (IEEE Trans. Computers, 2024)

Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs. - Divya Praneetha Ravipati; Victor M. van Santen; Shivendra Singh Parihar; Yogesh Singh Chauhan; Preeti Ranjan Panda; Hussam Amrouch (IEEE Trans. Computers, 2025)