Future generation supercomputers I: a paradigm for node architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Karthik Chandrasekar 001; Prem Kumar Ramesh; Viswanath Venkatesan; Arvindakshan Babu; Sudharshan (SIGARCH Comput. Archit. News, 2007)

Future generation supercomputers II: a paradigm for cluster architecture. - Nagarajan Venkateswaran; Deepak Srinivasan; Madhavan Manivannan; T. P. Ramnath Sai Sagar; Shyamsundar Gopalakrishnan; Vinoth Krishnan Elangovan; Arvind M; Prem Kumar Ramesh; Karthik Ganesan 006; Viswanath Krishnamurthy; Sivaramakrishnan (SIGARCH Comput. Archit. News, 2007)

Greedy Dynamic Crossover Management in Hardware Accelerated Genetic Algorithm Implementations Using FPGA. - Shubhalaxmi Kher; T. S. Ganesh; Prem Ramesh; Arun K. Somani (UKSim, 2009)

Managing contamination delay to improve Timing Speculation architectures. - Naga Durga Prasad Avirneni; Prem Kumar Ramesh; Arun K. Somani (PeerJ Prepr., 2016)

Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors. - Naga Durga Prasad Avirneni; Prem Kumar Ramesh; Arun K. Somani (IEEE Trans. Computers, 2016)

Towards a unified ontology for IoT fabric with SDDC. - Koundinya Koorapati; Rubini Pandu; Prem Kumar Ramesh; Sairam Veeraswamy; Usha Narasappa (J. King Saud Univ. Comput. Inf. Sci., 2022)