Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements - Douglas B. Armstrong; Arthur D. Friedman; Prem R. Menon (SWAT, 1967)

Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements. - Douglas B. Armstrong; Arthur D. Friedman; Premachandran R. Menon (IEEE Trans. Computers, 1968)

Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes. - Arthur D. Friedman; Prem R. Menon (IEEE Trans. Computers, 1968)

Design of Asynchronous Circuits Assuming Unbounded Gate Delays. - Douglas B. Armstrong; Arthur D. Friedman; Premachandran R. Menon (IEEE Trans. Computers, 1969)

Structural Simplification and Decomposition of Asynchronous Sequential Circuits. - Chung-Jen Tan; Premachandran R. Menon; Arthur D. Friedman (IEEE Trans. Computers, 1969)

On Sequential Machine Decompositions for Reducing the Number of Delay Elements - Premachandran R. Menon (Inf. Control., 1969)

Design of Generalized Double Rank and Multiple Rank Sequential Circuits - Arthur D. Friedman; Prem R. Menon (Inf. Control., 1969)

Systems of Asynchronously Operating Modules. - Arthur D. Friedman; Prem R. Menon (IEEE Trans. Computers, 1971)

Fault Detection in Iterative Logic Arrays. - Premachandran R. Menon; Arthur D. Friedman (IEEE Trans. Computers, 1971)

Comments on "Design of Diagnosable Iterative Arrays". - Arthur D. Friedman; Prem R. Menon (IEEE Trans. Computers, 1972)

Restricted Checking Sequences for Sequential Machines. - Arthur D. Friedman; Premachandran R. Menon (IEEE Trans. Computers, 1973)

Functional simulation in the lamp system. - Stephen G. Chappell; Prem R. Menon; John F. Pellegrin; A. M. Schowe (DAC, 1976)

Deductive Fault Simulation with Functional Blocks. - Premachandran R. Menon; Stephen G. Chappell (IEEE Trans. Computers, 1978)

Test Generation Algorithms for Computer Hardware Description Languages. - Ytzhak H. Levendel; Premachandran R. Menon (IEEE Trans. Computers, 1982)

Parallel fault simulation using distributed processing. - Ytzhak H. Levendel; Prem R. Menon; Suresh H. Patel (Bell Syst. Tech. J., 1983)

Totally Preset Checking Experiments for Sequential Machines. - Gordon K. Lin; Premachandran R. Menon (IEEE Trans. Computers, 1983)

A Logic Simulation Machine. - Miron Abramovici; Ytzhak H. Levendel; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

Critical Path Tracing: An Alternative to Fault Simulation. - Miron Abramovici; Prem R. Menon; David T. Miller (IEEE Des. Test, 1984)

Test Generation In Lamp2: System Overview. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (ITC, 1985)

Test Generation In Lamp2: Concepts and Algorithms. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (ITC, 1985)

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. - Miron Abramovici; Prem R. Menon (IEEE Trans. Computers, 1985)

SMART and FAST: Test Generation for VLSI Scan-Design Circuits. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (IEEE Des. Test, 1986)

Checkpoint Faults are not Sufficient Target Faults for Test Generation. - Miron Abramovici; Prem R. Menon; David T. Miller (IEEE Trans. Computers, 1986)

Critical path tracing in sequential circuits. - Prem R. Menon; Ytzhak H. Levendel; Miron Abramovici (ICCAD, 1988)

System-level design verification in the AT&T Computer Division: tools. - Miron Abramovici; James J. Kulikowski; David T. Miller; Prem R. Menon (ICCD, 1989)

Identification of undetectable faults in combinational circuits. - Mohan Harihara; Prem R. Menon (ICCD, 1989)

Symbolic Test Generation for Hierarchically Modeled Digital Systems. - P. N. Anirudhan; Premachandran R. Menon (ITC, 1989)

An Approach to Functional Level Testability Analysis. - C. H. Chen; Premachandran R. Menon (ITC, 1989)

Design of scan-testable CMOS sequential circuits. - Bong-Hee Park; Premachandran R. Menon (ITC, 1990)

Parallel pattern fault simulation based on stem faults in combinational circuits. - Ohyoung Song; Premachandran R. Menon (ITC, 1990)

Robustly Scan-Testable CMOS Sequential Circuits. - Bong-Hee Park; Premachandran R. Menon (ITC, 1991)

SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. - Premachandran R. Menon; Ytzhak H. Levendel; Miron Abramovici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Redundancy removal and simplification of combinational circuits. - Prem R. Menon; Hitesh Ahuja (VTS, 1992)

Stuck-open testable scan-based CMOS sequential circuits. - Bong-Hee Park; Premachandran R. Menon (IEEE J. Solid State Circuits, 1992)

Acceleration of trace-based fault simulation of combinational circuits. - Ohyoung Song; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

3-valued trace-based fault simulation of synchronous sequential circuits. - Ohyoung Song; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Divergence and scheduling in functional level concurrent fault simulation. - O. Y. Song; Bong-Hee Park; Prem R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Delay Reduction by Segment Substitution. - Hitesh Ajuha; Premachandran R. Menon (EDAC-ETC-EUROASIC, 1994)

Synthesis of Delay-Verifiable Two-Level Circuits. - Wuudiann Ke; Premachandran R. Menon (EDAC-ETC-EUROASIC, 1994)

Multi-level logic optimization by implication analysis. - Wolfgang Kunz; Prem R. Menon (ICCAD, 1994)

Delay-Verifiability of Combinational Circuits Based on Primitive Faults. - Wuudiann Ke; Premachandran R. Menon (ICCD, 1994)

Realization of fully path-delay-fault testable non-scan sequential circuits. - Wuudiann Ke; Premachandran R. Menon (VTS, 1994)

Redundancy identification and removal in combinational circuits. - Prem R. Menon; Hitesh Ahuja; Mohan Harihara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Multifault testability of delay-testable circuits. - Wuudiann Ke; Premachandran R. Menon (VTS, 1995)

Multifault and delay-fault testability of multilevel circuits. - Wuudiann Ke; Premachandran R. Menon (J. Electron. Test., 1995)

Synthesis of Delay-Verifiable Combinational Circuits. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Computers, 1995)

Path-delay-fault testable nonscan sequential circuits. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Delay-testable implementations of symmetric functions. - Wuudiann Ke; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Identifying Redundant Path Delay Faults in Sequential Circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (VLSI Design, 1996)

Fault simulation on reconfigurable hardware. - Miron Abramovici; Prem R. Menon (FCCM, 1997)

Test generation for primitive path delay faults in combinational circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCAD, 1997)

Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCD, 1997)

Delay Testing with Clock Control: An Alternative to Enhanced Scan. - Ramesh C. Tekumalla; Premachandran R. Menon (ITC, 1997)

Logic optimization and equivalence checking by implication analysis. - Wolfgang Kunz; Dominik Stoffel; Prem R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On primitive fault test generation in non-scan sequential circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCAD, 1998)

Robust testability of primitive faults using test points. - Ramesh C. Tekumalla; Premachandran R. Menon (ITC, 1999)

On Redundant Path Delay Faults in Synchronous Sequential Circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (IEEE Trans. Computers, 2000)

BIST-based delay path testing in FPGA architectures. - Ian G. Harris; Premachandran R. Menon; Russell Tessier (ITC, 2001)

Identification of primitive faults in combinational and sequentialcircuits. - Ramesh C. Tekumalla; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Design-specific path delay testing in lookup-table-based FPGAs. - Premachandran R. Menon; Weifeng Xu; Russell Tessier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)