An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects. - Pankaj Venuturupalli; Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (ISCAS, 2020)

A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (ISVLSI, 2020)

Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects. - Pankaj Venuturupalli; Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Microelectron. J., 2020)

A 27-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Circuits Syst. Signal Process., 2021)

Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects. - Prema Kumar Govindaswamy; Nijwm Wary; Vijaya Sankara Rao Pasupureddi (ISCAS, 2022)

A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects. - Prema Kumar Govindaswamy; Nijwm Wary; Vijaya Sankara Rao Pasupureddi (ISCAS, 2022)

A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects. - Prema Kumar Govindaswamy; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2022)

High-Swing, Power-efficient, Current-Mode Hybrid Circuit Topologies for Simultaneous Bidirectional Communication. - Prema Kumar Govindaswamy; P. Vijay Shankar (NEWCAS, 2023)

An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects. - Prema Kumar Govindaswamy; Raviteja Kammari; Vijaya Sankara Rao Pasupureddi (Int. J. Circuit Theory Appl., 2023)

A 0.2 pJ/bit, Energy-Efficient, Half-Rate Hybrid Circuit Topology at 6-Gb/s in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 27-1, 20-Gb/s, 0.1-pJ/b Pseudo Random Bit Sequence Generator Using Incomplete Settling in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 15-Gb/s, 0.036 pJ/bit, Half-Rate, Low Power PRBS Generator in 1.2 V, 65 nm CMOS. - Perakalapudi Ravibabu; Prema Kumar Govindaswamy; Vijay Shankar Pasupureddi (ISCAS, 2024)

A 0.186 pJ/bit, 6-Gb/s, Energy-Efficient, Half-Rate Hybrid Circuit Topology in 1.2V, 65 nm CMOS. - Prema Kumar Govindaswamy; Mursina Khatun; Vijay Shankar Pasupureddi (ISQED, 2024)

A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS. - Prema Kumar Govindaswamy; Nijwm Wary; Vijay Shankar Pasupureddi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)