Prem R. Menon

Affiliations:
  • University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA, USA
  • University of Washington, Seattle, WA, USA (1963)


According to our database1, Prem R. Menon authored at least 59 papers between 1967 and 2006.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1988, "For contributions to method of simulation and testing of digital circuits, and to switching theory.".

Timeline

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Bibliography

2006
Design-specific path delay testing in lookup-table-based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2001
Identification of primitive faults in combinational and sequentialcircuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

BIST-based delay path testing in FPGA architectures.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
On Redundant Path Delay Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers, 2000

1999
Robust testability of primitive faults using test points.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
On primitive fault test generation in non-scan sequential circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Logic optimization and equivalence checking by implication analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Delay Testing with Clock Control: An Alternative to Enhanced Scan.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Test generation for primitive path delay faults in combinational circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fault simulation on reconfigurable hardware.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
Identifying Redundant Path Delay Faults in Sequential Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
Delay-testable implementations of symmetric functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Path-delay-fault testable nonscan sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Synthesis of Delay-Verifiable Combinational Circuits.
IEEE Trans. Computers, 1995

Multifault and delay-fault testability of multilevel circuits.
J. Electron. Test., 1995

Multifault testability of delay-testable circuits.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994
Redundancy identification and removal in combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Realization of fully path-delay-fault testable non-scan sequential circuits.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Delay-Verifiability of Combinational Circuits Based on Primitive Faults.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Multi-level logic optimization by implication analysis.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Delay-Verifiable Two-Level Circuits.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Delay Reduction by Segment Substitution.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Divergence and scheduling in functional level concurrent fault simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

3-valued trace-based fault simulation of synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Acceleration of trace-based fault simulation of combinational circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Redundancy removal and simplification of combinational circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Robustly Scan-Testable CMOS Sequential Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Parallel pattern fault simulation based on stem faults in combinational circuits.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Design of scan-testable CMOS sequential circuits.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
An Approach to Functional Level Testability Analysis.
Proceedings of the Proceedings International Test Conference 1989, 1989

Symbolic Test Generation for Hierarchically Modeled Digital Systems.
Proceedings of the Proceedings International Test Conference 1989, 1989

Identification of undetectable faults in combinational circuits.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

System-level design verification in the AT&T Computer Division: tools.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
Critical path tracing in sequential circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1986
Checkpoint Faults are not Sufficient Target Faults for Test Generation.
IEEE Trans. Computers, 1986

SMART and FAST: Test Generation for VLSI Scan-Design Circuits.
IEEE Des. Test, 1986

1985
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults.
IEEE Trans. Computers, 1985

Test Generation In Lamp2: Concepts and Algorithms.
Proceedings of the Proceedings International Test Conference 1985, 1985

Test Generation In Lamp2: System Overview.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Critical Path Tracing: An Alternative to Fault Simulation.
IEEE Des. Test, 1984

1983
A Logic Simulation Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Totally Preset Checking Experiments for Sequential Machines.
IEEE Trans. Computers, 1983

Parallel fault simulation using distributed processing.
Bell Syst. Tech. J., 1983

1982
Test Generation Algorithms for Computer Hardware Description Languages.
IEEE Trans. Computers, 1982

1978
Deductive Fault Simulation with Functional Blocks.
IEEE Trans. Computers, 1978

1976
Functional simulation in the lamp system.
Proceedings of the 13th Design Automation Conference, 1976

1973
Restricted Checking Sequences for Sequential Machines.
IEEE Trans. Computers, 1973

1972
Comments on "Design of Diagnosable Iterative Arrays".
IEEE Trans. Computers, 1972

1971
Fault Detection in Iterative Logic Arrays.
IEEE Trans. Computers, 1971

Systems of Asynchronously Operating Modules.
IEEE Trans. Computers, 1971

1969
Design of Generalized Double Rank and Multiple Rank Sequential Circuits
Inf. Control., November, 1969

On Sequential Machine Decompositions for Reducing the Number of Delay Elements
Inf. Control., September, 1969

Structural Simplification and Decomposition of Asynchronous Sequential Circuits.
IEEE Trans. Computers, 1969

Design of Asynchronous Circuits Assuming Unbounded Gate Delays.
IEEE Trans. Computers, 1969

1968
Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes.
IEEE Trans. Computers, 1968

Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements.
IEEE Trans. Computers, 1968

1967
Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements
Proceedings of the 8th Annual Symposium on Switching and Automata Theory, 1967


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