Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. - Premkishore Shivakumar; Michael Kistler; Stephen W. Keckler; Doug Burger; Lorenzo Alvisi (DSN, 2002)

The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. - M. S. Hrishikesh; Doug Burger; Stephen W. Keckler; Premkishore Shivakumar; Norman P. Jouppi; Keith I. Farkas (ISCA, 2002)

Exploiting Microarchitectural Redundancy For Defect Tolerance. - Premkishore Shivakumar; Stephen W. Keckler; Charles R. Moore; Doug Burger (ICCD, 2003)

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. - Karthikeyan Sankaralingam; Ramadass Nagarajan; Robert G. McDonald; Rajagopalan Desikan; Saurabh Drolia; M. S. Govindan; Paul Gratz; Divya Gulati; Heather Hanson; Changkyu Kim; Haiming Liu 001; Nitya Ranganathan; et al. (MICRO, 2006)

Implementation and Evaluation of a Dynamically Routed Processor Operand Network. - Paul Gratz; Karthikeyan Sankaralingam; Heather Hanson; Premkishore Shivakumar; Robert G. McDonald; Stephen W. Keckler; Doug Burger (NOCS, 2007)

On-Chip Interconnection Networks of the TRIPS Chip. - Paul Gratz; Changkyu Kim; Karthikeyan Sankaralingam; Heather Hanson; Premkishore Shivakumar; Stephen W. Keckler; Doug Burger (IEEE Micro, 2007)