CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs. - Skyler Windh; Prerna Budhkar; Walid A. Najjar (ICCAD, 2015)

High-Level Language Tools for Reconfigurable Computing. - Skyler Windh; Xiaoyin Ma; Robert J. Halstead; Prerna Budhkar; Zabdiel Luna; Omar Hussaini; Walid A. Najjar (Proc. IEEE, 2015)

FPGA-accelerated group-by aggregation using synchronizing caches. - Ildar Absalyamov; Prerna Budhkar; Skyler Windh; Robert J. Halstead; Walid A. Najjar; Vassilis J. Tsotras (DaMoN, 2016)

Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques. - Prerna Budhkar (2018)

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. - Eriko Nurvitadhi; Mishali Naik; Andrew Boutros; Prerna Budhkar; Ali Jafari; Dongup Kwon; David Sheffield; Abirami Prabhakaran; Karthik Gururaj; Pranavi Appana (FPT, 2019)

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads. - Prerna Budhkar; Ildar Absalyamov; Vasileios Zois; Skyler Windh; Walid A. Najjar; Vassilis J. Tsotras (ACM Trans. Archit. Code Optim., 2019)

Efficient local locking for massively multithreaded in-memory hash-based operators. - Bashar Romanous; Skyler Windh; Ildar Absalyamov; Prerna Budhkar; Robert J. Halstead; Walid A. Najjar; Vassilis J. Tsotras (VLDB J., 2021)

CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder. - Prerna Budhkar; Navneet Rao; Jainaveen Sundaram; Tanay Karnik (ICIP, 2023)

A High-Performance Passive Base System for Distributed AI/Media Acceleration. - Ragh Kuttappa; Jainaveen Sundaram; Srivatsa Rangachar Srinivasa; Paolo A. Aseron; Gauthaman Murali; Vinayak Honkote; Prerna Budhkar; Dileep Kurian; Ronald Kalim; Thomas P. Thomas; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System. - Srivatsa Rangachar Srinivasa; Prerna Budhkar; Gauthaman Murali; Vui Seng Chua; Paolo A. Aseron; Vinayak Honkote; Ravi R. Iyer 001; Nilesh Jain; Dileep John Kurian; Anuradha Srinivasan; Tanay Karnik (CICC, 2025)

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Vinayak Honkote; Dan Lake; Jaykant Timbadiya; Satish Yada; Suresh Kadavakollu; James Greensky; Gauthaman Murali; Anuradha Srinivasan; et al. (ACM Great Lakes Symposium on VLSI, 2025)

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations. - Srivatsa Rangachar Srinivasa; Dileep Kurian; Paolo A. Aseron; Prerna Budhkar; Arun Radhakrishnan; Alejandro Cardenas Lopez; Jainaveen Sundaram; Vinayak Honkote; Leonid Azarenkov; Dan Lake; Jaykant Timbadiya; Mikhail J. Moiseev; et al. (ISSCC, 2025)