How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. - Prianka Sengupta; Aakash Tyagi; Yiran Chen 001; Jiang Hu (ICCAD, 2022)

Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction. - Prianka Sengupta; Aakash Tyagi; Yiran Chen 001; Jiang Hu (MLCAD, 2023)

MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network. - Prianka Sengupta; Aakash Tyagi; Jiang Hu; Vivek K. Rajan; Hesham Mostafa; Somdeb Majumdar (MLCAD, 2024)

Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language. - Runzhi Wang 005; Prianka Sengupta; Yiran Chen 001; Jiang Hu (CoRR, 2025)