LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. - Pritam Bhattacharjee; Alak Majumder (iNIS, 2016)

A 90 nm leakage control transistor based clock gating for low power flip flop applications. - Pritam Bhattacharjee; Alak Majumder; Tushar Dhabal Das (MWSCAS, 2016)

Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. - Alak Majumder; Pritam Bhattacharjee (iNIS, 2017)

Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell. - Pritam Bhattacharjee; Kunal Das; Arijit Dey; Debashis De; Swarnendu Kumar Chakraborty (J. Low Power Electron., 2017)

LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. - Pritam Bhattacharjee; Bipasha Nath; Alak Majumder (CoRR, 2018)

Data-Dependent Clock Gating approach for Low Power Sequential System. - Dhiraj Sarkar; Pritam Bhattacharjee; Alak Majumder (CoRR, 2018)

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. - Alak Majumder; Pritam Bhattacharjee; Tushar Dhabal Das (J. Circuits Syst. Comput., 2018)

A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. - Pritam Bhattacharjee; Alak Majumder (J. Circuits Syst. Comput., 2019)

A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. - Pritam Bhattacharjee; Bidyut K. Bhattacharyya; Alak Majumder (Circuits Syst. Signal Process., 2021)

Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. - Pritam Bhattacharjee; Prerna Rana; Bidyut K. Bhattacharyya; Alak Majumder (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. - Pritam Bhattacharjee; G. Naveen Goud; Vipin Kumar Singh 002; Vijay Pratap Yadav; Abir J. Mondal; Alak Majumder (RADIOELEKTRONIKA, 2023)

Exploring the Application of Variable Frequency Clock as the Constituent of OCT. - Priyanka J; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

An Algorithmic Approach of Generating a VFC of Low Average Frequency Ramp. - Priyanka J; Ankita Deb; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

A Method of Variable Frequency Clock Generation. - Vipin Kumar Singh 002; Vijay Pratap Yadav; Tika Ram Pokhrel; Pritam Bhattacharjee; Alak Majumder (iSES, 2024)

Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. - Pritam Bhattacharjee; Alak Majumder (VLSID, 2024)