Fast FPGA Placement using Space-filling Curve. - Pritha Banerjee 001; Subhasis Bhattacharjee; Susmita Sur-Kolay; Sandip Das 001; Subhas C. Nandy (FPL, 2005)

Faster Placer for Island-Style FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay (ICCTA, 2007)

Floorplanning in Modern FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu (VLSI Design, 2007)

Floorplanning for Partial Reconfiguration in FPGAs. - Pritha Banerjee 001; Megha Sangtani; Susmita Sur-Kolay (VLSI Design, 2009)

Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

FPGA placement using space-filling curves: Theory meets practice. - Pritha Banerjee 001; Susmita Sur-Kolay; Arijit Bishnu; Sandip Das 001; Subhas C. Nandy; Subhasis Bhattacharjee (ACM Trans. Embed. Comput. Syst., 2009)

Cone-based placement for field programmable gate arrays. - Pritha Banerjee 001; Debasri Saha; Susmita Sur-Kolay (IET Comput. Digit. Tech., 2011)

Floorplanning for Partially Reconfigurable FPGAs. - Pritha Banerjee 001; Megha Sangtani; Susmita Sur-Kolay (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

An efficient and effective analytical placer for FPGAs. - Tzu-Hen Lin; Pritha Banerjee 001; Yao-Wen Chang (DAC, 2013)

Flare reduction in EUV Lithography by perturbation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSI-SoC, 2015)

Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ICCD, 2017)

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (ISVLSI, 2019)

A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. - Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (IET Circuits Devices Syst., 2021)

Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. - Kritanta Saha; Pritha Banerjee 001; Susmita Sur-Kolay (VLSI-SoC, 2022)

Stitch-avoiding Global Routing for Multiple E-Beam Lithography. - Kritanta Saha; Sudipta Paul 001; Pritha Banerjee 001; Susmita Sur-Kolay (VLSID, 2022)

Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. - Sudipta Paul 001; Tridib Mukherjee; Pritha Banerjee 001; Susmita Sur-Kolay (Integr., 2023)

Constructing Rectilinear Steiner Minimum Tree with Conditional Generative Adversarial Network. - Kritanta Saha; Pritha Banerjee 001; Susmita Sur-Kolay (VLSID, 2025)