8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen Kim; Yutao Liu; Savyassachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (ISSCC, 2021)

11.5 A 23.9-to-29.4GHz Digital LC-PLL with a Coupled Frequency Doubler for Wireline Applications in 10nm FinFET. - Dongseok Shin; Hyung Seok Kim; Chuanchang Liu; Priya Wali; Savyasaachi Keshava Murthy; Yongping Fan (ISSCC, 2021)

A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS. - Shiva Kiran; Ajay Balankutty; Yutao Liu; Rajeev Dokania; Hariprasath Venkataraman; Priya Wali; Stephen Kim; Yoel Krupnik; Ariel Cohen 001; Frank O'Mahony (VLSI Circuits, 2021)

A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET. - Jihwan Kim; Sandipan Kundu; Ajay Balankutty; Matthew Beach; Bong Chan Kim; Stephen T. Kim; Yutao Liu; Savyasaachi Keshava Murthy; Priya Wali; Kai Yu 016; Hyung Seok Kim; Chuanchang Liu; et al. (IEEE J. Solid State Circuits, 2022)

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications. - Dongseok Shin; Hyung Seok Kim; Chuanchang Liu; Priya Wali; Savyasaachi Keshava Murthy; Yongping Fan (IEEE J. Solid State Circuits, 2022)

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging. - Jihwan Kim; Ariel Cohen 001; Mike Peng Li; Ajay Balankutty; Sandipan Kundu; Ahmad Khairi; Yoel Krupnik; Yoav Segal; Marco Cusmai; Dror Lazar; Ari Gordon; Noam Familia; et al. (CICC, 2024)