An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. - Srinivasulu Alampally; R. T. Venkatesh; Priyadharshini Shanmugasundaram; Rubin A. Parekhji; Vishwani D. Agrawal (VTS, 2011)

Dynamic scan clock control for test time reduction maintaining peak power limit. - Priyadharshini Shanmugasundaram; Vishwani D. Agrawal (VTS, 2011)

Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. - Priyadharshini Shanmugasundaram; Vishwani D. Agrawal (VLSI Design, 2012)