Tradeoffs between settling time and jitter in phase locked loops. - Pallavi Paliwal; Priyank Laad; Mohanrao Sattineni; Shalabh Gupta (MWSCAS, 2013)

High resolution digital-to-time converter for low jitter digital PLLs. - Anil Chawda; Pallavi Paliwal; Priyank Laad; Shalabh Gupta (ICECS, 2014)