Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm. - Priyanka Choudhury; Sambhu Nath Pradhan (VDAT, 2012)

An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together. - Priyanka Choudhury; Sambhu Nath Pradhan (J. Low Power Electron., 2012)

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (VDAT, 2013)

Power gating architecture implementation inside clock period to reduce power. - Debanjali Nath; Priyanka Choudhury; Abhishek Nag; Sambhu Nath Pradhan (Int. J. Comput. Aided Eng. Technol., 2014)

Thermal aware AND-OR-XOR network synthesis. - Priyanka Choudhury; Debanjali Nath; Vivek Rai; Sambhu Nath Pradhan (VDAT, 2015)

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2016)

Transistor level realisation of power gated FSM. - Sambhu Nath Pradhan; Priyanka Choudhury; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2017)

Thermal-Aware Partitioning and Encoding of Power-Gated FSM. - Priyanka Choudhury; Kanchan Manna; Vivek Rai; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2019)