Reconfigurable processor for energy-scalable computational photography. - Rahul Rithe; Priyanka Raina; Nathan Ickes; Srikanth V. Tenneti; Anantha P. Chandrakasan (ISSCC, 2013)

Reconfigurable Processor for Energy-Efficient Computational Photography. - Rahul Rithe; Priyanka Raina; Nathan Ickes; Srikanth V. Tenneti; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2013)

Correction to "Reconfigurable Processor for Energy-Efficient Computational Photography". - Rahul Rithe; Priyanka Raina; Nathan Ickes; Srikanth V. Tenneti; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2014)

24.1 A 0.6V 8mW 3D vision processor for a navigation device for the visually impaired. - Dongsuk Jeon; Nathan Ickes; Priyanka Raina; Hsueh-Cheng Wang; Daniela Rus; Anantha P. Chandrakasan (ISSCC, 2016)

An Energy-Scalable Accelerator for Blind Image Deblurring. - Priyanka Raina; Mehul Tikekar; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2017)

Energy-efficient circuits and systems for computational imaging and vision on mobile devices. - Priyanka Raina (2018)

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. - Rangharajan Venkatesan; Yakun Sophia Shao; Brian Zimmer; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Hot Chips Symposium, 2019)

MAGNet: A Modular Accelerator Generator for Neural Networks. - Rangharajan Venkatesan; Yakun Sophia Shao; Miaorong Wang; Jason Clemons; Steve Dai; Matthew Fojtik; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Yanqing Zhang 002; Brian Zimmer; et al. (ICCAD, 2019)

Timeloop: A Systematic Approach to DNN Accelerator Evaluation. - Angshuman Parashar; Priyanka Raina; Yakun Sophia Shao; Yu-Hsin Chen; Victor A. Ying; Anurag Mukkara; Rangharajan Venkatesan; Brucek Khailany; Stephen W. Keckler; Joel S. Emer (ISPASS, 2019)

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (MICRO, 2019)

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (VLSI Circuits, 2019)

Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks. - Makena Low; Priyanka Raina (CoRR, 2019)

Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators. - Xuan Yang; Mingyu Gao 001; Qiaoyi Liu; Jeff Setter; Jing Pu; Ankita Nayak; Steven Bell; Kaidi Cao; Heonjae Ha; Priyanka Raina; Christos Kozyrakis; Mark Horowitz (ASPLOS, 2020)

Creating an Agile Hardware Design Flow. - Rick Bahr; Clark W. Barrett; Nikhil Bhagdikar; Alex Carsello; Ross Daly; Caleb Donovick; David Durst; Kayvon Fatahalian; Kathleen Feng; Pat Hanrahan; Teguh Hofstee; Mark Horowitz; et al. (DAC, 2020)

A-QED Verification of Hardware Accelerators. - Eshan Singh; Florian Lonsing; Saranyu Chattopadhyay; Maxwell Strange; Peng Wei 004; Xiaofan Zhang 001; Yuan Zhou; Deming Chen; Jason Cong; Priyanka Raina; Zhiru Zhang; Clark W. Barrett; et al. (DAC, 2020)

A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (DATE, 2020)

Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks. - Makena Low; Victor Huang; Priyanka Raina (ISBI, 2020)

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. - Weier Wan; Rajkumar Kubendran; Sukru Burc Eryilmaz; Wenqiang Zhang; Yan Liao; Dabin Wu; Stephen R. Deiss; Bin Gao 006; Priyanka Raina; Siddharth Joshi 001; Huaqiang Wu; Gert Cauwenberghs; et al. (ISSCC, 2020)

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. - Brian Zimmer; Rangharajan Venkatesan; Yakun Sophia Shao; Jason Clemons; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (IEEE J. Solid State Circuits, 2020)

Simba: scaling deep-learning inference with chiplet-based architecture. - Yakun Sophia Shao; Jason Clemons; Rangharajan Venkatesan; Brian Zimmer; Matthew Fojtik; Nan Jiang 009; Ben Keller; Alicia Klinefelter; Nathaniel Ross Pinckney; Priyanka Raina; Stephen G. Tell; Yanqing Zhang 002; et al. (Commun. ACM, 2021)

Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis. - Jackson Melchert; Kathleen Feng; Caleb Donovick; Ross Daly; Clark W. Barrett; Mark Horowitz; Pat Hanrahan; Priyanka Raina (CoRR, 2021)

Compiling Halide Programs to Push-Memory Accelerators. - Qiaoyi Liu; Dillon Huff; Jeff Setter; Maxwell Strange; Kathleen Feng; Kavya Sreedhar; Ziheng Wang; Keyi Zhang; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (CoRR, 2021)

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (CoRR, 2021)

Enabling Reusable Physical Design Flows with Modular Flow Generators. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (CoRR, 2021)

Best Papers From Hot Chips 32. - Priyanka Raina; Cliff Young (IEEE Micro, 2021)

Efficient Routing in Coarse-Grained Reconfigurable Arrays Using Multi-Pole NEM Relays. - Akash Levy; Michael Oduoza; Akhilesh Balasingam; Roger T. Howe; Priyanka Raina (ASP-DAC, 2022)

mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. - Alex Carsello; James Thomas 003; Ankita Nayak; Po-Han Chen; Mark Horowitz; Priyanka Raina; Christopher Torng (DAC, 2022)

Synthesizing Instruction Selection Rewrite Rules from RTL using SMT. - Ross Daly; Caleb Donovick; Jackson Melchert; Rajsekhar Setaluri; Nestan Tsiskaridze; Priyanka Raina; Clark W. Barrett; Pat Hanrahan (FMCAD, 2022)

Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. - Kathleen Feng; Alex Carsello; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (HCS, 2022)

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Alex Carsello; Kathleen Feng; Taeyoung Kong; Kalhan Koul; Qiaoyi Liu; Jackson Melchert; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (VLSI Technology and Circuits, 2022)

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. - Kartik Prabhu; Albert Gural; Zainab F. Khan; Robert M. Radway; Massimo Giordano; Kalhan Koul; Rohan Doshi; John W. Kustin; Timothy Liu; Gregorio B. Lopes; Victor Turbiner; Win-San Khwa; et al. (IEEE J. Solid State Circuits, 2022)

A compute-in-memory chip based on resistive random-access memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (Nat., 2022)

High-density analog image storage in an analog-valued non-volatile memory array. - Xin Zheng 013; Ryan Zarcone; Akash Levy; Win-San Khwa; Priyanka Raina; Bruno A. Olshausen; H.-S. Philip Wong (Neuromorph. Comput. Eng., 2022)

APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis. - Jackson Melchert; Kathleen Feng; Caleb Donovick; Ross Daly; Ritvik Sharma; Clark W. Barrett; Mark A. Horowitz; Pat Hanrahan; Priyanka Raina (ASPLOS (3), 2023)

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits. - Tathagata Srimani; Robert M. Radway; Jinwoo Kim; Kartik Prabhu; Dennis Rich; Carlo Gilardi; Priyanka Raina; Max M. Shulaker; Sung Kyu Lim; Subhasish Mitra (DATE, 2023)

EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry. - Luke R. Upton; Akash Levy; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina; Boris Murmann (ESSCIRC, 2023)

PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM. - Anjiang Wei; Akash Levy; Pu Yi 001; Robert M. Radway; Priyanka Raina; Subhasish Mitra; Sara Achour (ICCAD, 2023)

An Open-Source $4 times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow. - Po-Han Chen; Charles Tsao; Priyanka Raina (ISCAS, 2023)

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays. - Jackson Melchert; Keyi Zhang; Yuchen Mei; Mark Horowitz; Christopher Torng; Priyanka Raina (IEEE Comput. Archit. Lett., 2023)

Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays. - Taeyoung Kong; Kalhan Koul; Priyanka Raina; Mark Horowitz; Christopher Torng (CoRR, 2023)

PEak: A Single Source of Truth for Hardware Design and Verification. - Caleb Donovick; Ross Daly; Jackson Melchert; Lenny Truong; Priyanka Raina; Pat Hanrahan; Clark W. Barrett (CoRR, 2023)

3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing. - Akash Levy; Michael Oduoza; Akhilesh Balasingam; Roger T. Howe; Priyanka Raina (Integr., 2023)

GeneFriends: gene co-expression databases and tools for humans and model organisms. - Priyanka Raina; Rodrigo Guinea; Kasit Chatsirisupachai; Inês Lopes; Zoya Farooq; Cristina Guinea; Csaba-Attila Solyom; João Pedro de Magalhães (Nucleic Acids Res., 2023)

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. - Kalhan Koul; Jackson Melchert; Kavya Sreedhar; Leonard Truong; Gedeon Nyengele; Keyi Zhang; Qiaoyi Liu; Jeff Setter; Po-Han Chen; Yuchen Mei; Maxwell Strange; Ross Daly; et al. (ACM Trans. Embed. Comput. Syst., 2023)

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators. - Qiaoyi Liu; Jeff Setter; Dillon Huff; Maxwell Strange; Kathleen Feng; Mark Horowitz; Priyanka Raina; Fredrik Kjolstad (ACM Trans. Archit. Code Optim., 2023)

Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. - Ankita Nayak; Keyi Zhang; Rajsekhar Setaluri; Alex Carsello; Makai Mann; Christopher Torng; Stephen Richardson; Rick Bahr; Pat Hanrahan; Mark Horowitz; Priyanka Raina (ACM Trans. Reconfigurable Technol. Syst., 2023)

8-bit Transformer Inference and Fine-tuning for Edge Accelerators. - Jeffrey Yu; Kartik Prabhu; Yonatan Urman; Robert M. Radway; Eric Han; Priyanka Raina (ASPLOS (3), 2024)

Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection. - Ross Daly; Caleb Donovick; Caleb Terrill; Jackson Melchert; Priyanka Raina; Clark W. Barrett; Pat Hanrahan (FMCAD, 2024)

Onyx: A Programmable Accelerator for Sparse Tensor Algebra. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (HCS, 2024)

FastPASE: An AI-Driven Fast PPA Speculation Engine for RTL Design Space Optimization. - Akash Levy; Joe Walston; Sourav Samanta; Priyanka Raina; Stelios Diamantidis (ISQED, 2024)

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. - Kalhan Koul; Maxwell Strange; Jackson Melchert; Alex Carsello; Yuchen Mei; Olivia Hsu; Taeyoung Kong; Po-Han Chen; Huifeng Ke; Keyi Zhang; Qiaoyi Liu; Gedeon Nyengele; et al. (VLSI Technology and Circuits, 2024)

MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating. - Kartik Prabhu; Robert M. Radway; Y. Jeffrey; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (VLSI Technology and Circuits, 2024)

Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. - Kathleen Feng; Taeyoung Kong; Kalhan Koul; Jackson Melchert; Alex Carsello; Qiaoyi Liu; Gedeon Nyengele; Maxwell Strange; Keyi Zhang; Ankita Nayak; Jeff Setter; James Thomas 003; et al. (IEEE J. Solid State Circuits, 2024)

EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage. - Akash Levy; Luke R. Upton; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Boris Murmann; Priyanka Raina (IEEE J. Solid State Circuits, 2024)

Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays. - Jackson Melchert; Yuchen Mei; Kalhan Koul; Qiaoyi Liu; Mark Horowitz; Priyanka Raina (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications. - Po-Han Chen; Bo-Wun Cheng; Michael Oduoza; Zhouhua Xie; Kalhan Koul; Sai Gautham Ravipati; Yuchen Mei; Rupert Lu; Alex Carsello; Mark Horowitz; Priyanka Raina (CICC, 2025)

Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads. - Kathleen Feng; Kartik Prabhu; Kai Bartolone; Jeffrey Yu; Priyanka Raina (CICC, 2025)

Designing Programmable Accelerators for Sparse Tensor Algebra. - Kalhan Koul; Zhouhua Xie; Maxwell Strange; Sai Gautham Ravipati; Bo-Wun Cheng; Olivia Hsu; Po-Han Chen; Mark Horowitz; Fredrik Kjolstad; Priyanka Raina (IEEE Micro, 2025)

MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator. - Kartik Prabhu; Robert M. Radway; Jeffrey Yu; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (IEEE J. Solid State Circuits, 2025)