Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. - Gaetano Palumbo; Giuseppe Introvaia; Vincenzo Mastrocola; Promod Kumar; Francesco Pipiton (IOLTW, 2001)

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs. - Anuj Grover; Promod Kumar; Mohammad Daud; G. S. Visweswaran; Chittoor R. Parthasarathy; Jean-Philippe Noel; David Turgis; Bastien Giraud; Guillaume Moritz (ICICDT, 2015)

FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems. - Amit Chhabra; Harsh Rawat; Mohit Jain; Pascal Tessier; Daniel Pierredon; Laurent Bergher; Promod Kumar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

High-yield design of high-density SRAM for low-voltage and low-leakage operations. - Kedar Janardan Dhori; Hitesh Chawla; Ashish Kumar; Prashant Pandey; Promod Kumar; Lorenzo Ciampolini; Florian Cacho; Damien Croain (DFT, 2017)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. - Kedar Janardan Dhori; Promod Kumar; Christophe Lecocq; Pascal Urard; Olivier Callen; Florian Cacho; Maryline Parra; Prashant Pandey; Daniel Noblet (VLSID, 2022)