Design and Implementation of Optimized Register File for Streaming Applications. - Ayazulla Khan Patan; Dimitrios Stathis 001; Pudi Dhilleswararao; Yu Yang; Srinivas Boppu; Ahmed Hemani (VDAT, 2021)

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey. - Pudi Dhilleswararao; Srinivas Boppu; M. Sabarimalai Manikandan; Linga Reddy Cenkeramaddi (IEEE Access, 2022)

Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Vamsi Goudu; Srinivas Boppu; Ahmed Hemani (DSD, 2023)

Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Rajeev Ryansh; Srinivas Boppu; Yu Yang; Ahmed Hemani (HEART, 2023)

Implementation of Image Averaging on DRRA and DiMArch Architectures. - Pudi Dhilleswararao; Vamsi Goudu; Srinivas Boppu; Ritika Ratnu; Ahmed Hemani (SBCCI, 2023)

Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. - Ashish Reddy Bommana; Susheel Ujwal Siddamshetty; Pudi Dhilleswararao; Arvind Thumatti K. R.; Srinivas Boppu; M. Sabarimalai Manikandan; Linga Reddy Cenkeramaddi (ACM Trans. Design Autom. Electr. Syst., 2023)

Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. - Pudi Dhilleswararao; Shivam Malviya; Srinivas Boppu; Yu Yang; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. - Pudi Dhilleswararao; Yu Yang; Dimitrios Stathis 001; Sunil Kumar Prajapati; Srinivas Boppu; Ahmed Hemani; Linga Reddy Cenkeramaddi (IEEE Access, 2024)

Automating functional unit and register binding for synchoros CGRA platform. - Pudi Dhilleswararao; Utsav Tiwari; Srinivas Boppu; Yu Yang; Ahmed Hemani (Des. Autom. Embed. Syst., 2024)