Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver. - Pui-In Mak; Chi-sam Sou; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. - Pui-In Mak; Kin-Kwan Ma; Weng-leng Mok; Chi-sam Sou; Kit-man Ho; Cheng-Man Ng; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2004)

A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. - Pui-In Mak; Man-Chung Wong; Seng-Pan U. (ISCAS (5), 2004)

A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (CICC, 2005)

A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. - Ka-Hou Ao Ieong; Chong-Yin Fok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2005)

Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. - Weng-leng Mok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2007)

Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2007)

A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers. - Ka-Fai Un; Pui-In Mak; Rui Paulo da Silva Martins (APCCAS, 2008)

An open-source-input, ultra-wideband LNA with mixed-voltage ESD protection for full-band (170-to-1700 MHz) mobile TV tuners. - Pui-In Mak; Ka-Hou Ao Ieong; Rui Paulo Martins (ISCAS, 2008)

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 90nm CMOS Bio-potential Signal Readout Front-end with Improved Powerline Interference Rejection. - Chon-Teng Ma; Pui-In Mak; Mang I Vai; Peng Un Mak; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (ISCAS, 2009)

An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2009)

Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners. - Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Source-follower-based bi-quad cell for continuous-time zero-pole type filters. - Yong Chen 005; Pui-In Mak; Yumei Zhou (ISCAS, 2010)

SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit. - Miguel A. Martins; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ISCAS, 2010)

Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An ultra-low-power filtering technique for biomedical applications. - Tan-Tan Zhang; Pui-In Mak; Mang I Vai; Peng Un Mak; Feng Wan; Rui Paulo Martins (EMBC, 2011)

A highly-linear ultra-wideband balun-LNA for cognitive radios. - Weng-Fai Cheng; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (EUROCON, 2011)

Entropy penalized learning for Gaussian mixture models. - Boyu Wang 004; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai (IJCNN, 2011)

A Solution to harmonic frequency problem: Frequency and phase coding-based brain-computer interface. - Chiman Wong; Boyu Wang 004; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai (IJCNN, 2011)

A high-voltage-enabled recycling folded cascode OpAmp for nanoscale CMOS technologies. - Miao Liu; Pui-In Mak; Zushu Yan; Rui Paulo Martins (ISCAS, 2011)

A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance. - Miguel A. Martins; Pui-In Mak; Rui Paulo Martins (ISCAS, 2011)

A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS. - Pui-In Mak; Rui Paulo Martins (ISSCC, 2011)

Robust Learning of Mixture Models and Its Application on Trial Pruning for EEG Signal Analysis. - Boyu Wang 004; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai (PAKDD Workshops, 2011)

A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS. - Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2011)

A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation. - Yinsidi Jiao; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2012)

A 0.8 µW 8-bit 1.5∼20-pF-input-range capacitance-to-digital converter for lab-on-chip digital microfluidics systems. - Yanjie Xiao; Tan-Tan Zhang; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (BioCAS, 2012)

Object Recognition Test in Peripheral Vision: A Study on the Influence of Object Color, Pattern and Shape. - Chin Ian Lou; Daria Migotina; João P. Rodrigues; João D. Semedo; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai; Fernando Melicio; J. Gomes Pereira; Agostinho C. Rosa (Brain Informatics, 2012)

Flashing color on the performance of SSVEP-based brain-computer interfaces. - Teng Cao; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai; Yong Hu 003 (EMBC, 2012)

A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier. - Miguel A. Martins; Pui-In Mak; Rui Paulo Martins (ISCAS, 2012)

A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISSCC, 2012)

Implementation of SSVEP based BCI with Emotiv EPOC. - Yue Liu; Xiao Jiang; Teng Cao; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai (VECIMS, 2012)

Neurofeedback for the treatment of schizophrenia: Case study. - Wenya Nan; Lanshin Chang; João P. Rodrigues; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai; Agostinho C. Rosa (VECIMS, 2012)

Trial pruning based on genetic algorithm for single-trial EEG classification. - Boyu Wang 004; Chiman Wong; Feng Wan; Peng Un Mak; Pui-In Mak; Mang I Vai (Comput. Electr. Eng., 2012)

A 0.83-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform for Wireless ECG Acquisition in 0.35-µm CMOS. - Chio-In Ieong; Pui-In Mak; Chi-Pang Lam; Cheng Dong; Mang I Vai; Peng Un Mak; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2012)

Sub-threshold standard cell library design for ultra-low power biomedical applications. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Rui Paulo Martins (EMBC, 2013)

A 0.5V 10GHz 8-phase LC-VCO Combining current-reuse and back-gate-coupling techniques consuming 2mW. - Md. Tawfiq Amin; Pui-In Mak; Rui Paulo Martins (ISCAS, 2013)

A 1.83 μW, 0.78 μVrms input referred noise neural recording front end. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2013)

Canonical Correlation Analysis Neural Network for Steady-State Visual Evoked Potentials Based Brain-Computer Interfaces. - Ka Fai Lao; Chiman Wong; Feng Wan; Pui-In Mak; Peng Un Mak; Mang I Vai (ISNN (2), 2013)

A 1.7mW 0.22mm2 2.4GHz ZigBee RX exploiting a current-reuse blixer + hybrid filter topology in 65nm CMOS. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2013)

A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS. - Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

Correction to "A 0.016 mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW". - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

15-nW Biopotential LPFs in 0.35-µm CMOS Using Subthreshold-Source-Follower Biquads With and Without Gain Compensation. - Tan-Tan Zhang; Pui-In Mak; Mang I Vai; Peng Un Mak; Man-Kay Law; Sio-Hang Pun; Feng Wan; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2013)

A Single-Branch Third-Order Pole-Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability. - Yong Chen 005; Pui-In Mak; Stefano D'Amico; Li Zhang 046; He Qian; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm2 Die Size in 90-nm CMOS. - Yong Chen 005; Pui-In Mak; Li Zhang 046; He Qian; Yan Wang 023 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware. - Wei-Han Yu; Chak-Fong Cheang; Pui-In Mak; Weng-Fai Cheng; Ka-Fai Un; U-Wai Lok; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level. - Shiheng Yang; Pui-In Mak; Rui Paulo Martins (APCCAS, 2014)

Design considerations of a low-noise receiver front-end and its spiral coil for portable NMR screening. - Diyang Zhao; Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (APCCAS, 2014)

Micropower two-stage amplifier employing recycling current-buffer Miller compensation. - Wei Wang 177; Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISCAS, 2014)

A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout. - Suyan Fan; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISIC, 2014)

3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF. - Fujian Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2014)

9.4 A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2014)

17.2 A 0.0013mm2 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins; Franco Maloberti (ISSCC, 2014)

Muscle and electrode motion artifacts reduction in ECG using adaptive Fourier decomposition. - Ze Wang 001; Chiman Wong; Janir Nuno da Cruz; Feng Wan; Pui-In Mak; Peng Un Mak; Mang I Vai (SMC, 2014)

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability. - Pui-In Mak; Miao Liu; Yaohua Zhao; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2014)

A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF. - Fujian Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2014)

Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Predicting favorable protein docking poses on a solid surface by particle swarm optimization. - Jimmy C. F. Ngai; Pui-In Mak; Shirley W. I. Siu (CEC, 2015)

Beta/theta ratio neurofeedback training effects on the spectral topography of EEG. - Limin Yang; Wenya Nan; Xiaoting Qu; Feng Wan; Pui-In Mak; Peng Un Mak; Mang I Vai; Yong Hu 003; Agostinho C. Rosa (EMBC, 2015)

2.4 A 0.028mm2 11mW single-mixing blocker-tolerant receiver with double-RF N-path filtering, S11 centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF. - Zhicheng Lin; Pui-In Mak; Rui Paulo Martins (ISSCC, 2015)

A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS. - Md. Tawfiq Amin; Pui-In Mak; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2015)

Corrections to "A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad". - P. V. Ananda Mohan; Yaohua Zhao; Pui-In Mak; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate. - Zushu Yan; Pui-In Mak; Man-Kay Law; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

A 0.02 mm2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad. - Yaohua Zhao; Pui-In Mak; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2015)

A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth. - Chak-Fong Cheang; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 0.0045-mm2 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation. - Zushu Yan; Wei Wang 177; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. - Yong Chen 005; Pui-In Mak; Yan Wang 023 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Sio-Hang Pun; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area. - Yaohua Zhao; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter. - Chak-Fong Cheang; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (ASP-DAC, 2016)

Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring. - Chio-In Ieong; Pui-In Mak; Mang I Vai; Rui Paulo Martins (ASP-DAC, 2016)

Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. - Mingzhong Li; Chio-In Ieong; Man-Kay Law; Pui-In Mak; Mang I Vai; Sio-Hang Pun; Rui Paulo Martins (ASP-DAC, 2016)

A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISCAS, 2016)

28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays. - Ka-Meng Lei; Hadi Heidari; Pui-In Mak; Man-Kay Law; Franco Maloberti; Rui Paulo Martins (ISSCC, 2016)

26.9 A 0.038mm2 SAW-less multiband transceiver using an N-Path SC gain loop. - Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (ISSCC, 2016)

2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ISSCC, 2016)

ProtPOS: a python package for the prediction of protein preferred orientation on a surface. - Jimmy C. F. Ngai; Pui-In Mak; Shirley W. I. Siu (Bioinform., 2016)

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell. - Suyan Fan; Man-Kay Law; Mingzhong Li; Zhiyuan Chen 002; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (J. Circuits Syst. Comput., 2016)

A µNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output. - Jun Yin 001; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. - Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISCAS, 2017)

Piecewise BJT process spread compensation exploiting base recombination current. - Dapeng Sun; Man-Kay Law; Bo Wang 012; Pui-In Mak; Rui Paulo Martins (ISCAS, 2017)

22.2 A 1.7mm2 inductorless fully integrated flipping-capacitor rectifier (FCR) for piezoelectric energy harvesting with 483% power-extraction enhancement. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Wing-Hung Ki; Rui Paulo Martins (ISSCC, 2017)

Session 21 overview: Smart SoCs for innovative applications. - Antoine Dupret; Pui-In Mak; Eugenio Cantatore (ISSCC, 2017)

24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. - Wei-Han Yu; Haidong Yi; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2017)

Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Wing-Hung Ki; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays. - Ka-Meng Lei; Hadi Heidari; Pui-In Mak; Man-Kay Law; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) Pout. - Xingqiang Peng; Jun Yin 001; Pui-In Mak; Wei-Han Yu; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A 0.038-mm2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop. - Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A Single-Chip Solar Energy Harvesting IC Using Integrated Photodiodes for Biomedical Implant Applications. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Biomed. Circuits Syst., 2017)

An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation. - Chang-Hao Chen; Elizabeth A. McCullagh; Sio-Hang Pun; Peng Un Mak; Mang I Vai; Pui-In Mak; Achim Klug; Tim C. Lei (IEEE Trans. Biomed. Eng., 2017)

A 73.9%-Efficiency CMOS Rectifier Using a Lower DC Feeding (LDCF) Self-Body-Biasing Technique for Far-Field RF Energy-Harvesting Systems. - Amin Khalili Moghaddam; Joon Huang Chuah; Harikrishnan Ramiah; Jalil Ahmadian; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement. - Wei-Han Yu; Xingqiang Peng; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures. - Chio-In Ieong; Mingzhong Li; Man-Kay Law; Pui-In Mak; Mang I Vai; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (A-SSCC, 2018)

A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISCAS, 2018)

A 0.22-to-2.4V-input fine-grained fully integrated rational buck-boost SC DC-DC converter using algorithmic voltage-feed-in (AVFI) topology achieving 84.1% peak efficiency at 13.2mW/mm2. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (ISSCC, 2018)

An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM. - Chee-Cheow Lim; Jun Yin 001; Pui-In Mak; Harikrishnan Ramiah; Rui Paulo Martins (ISSCC, 2018)

A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. - Jun Yin 001; Shiheng Yang; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2018)

Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2018)

Guest Editorial Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications. - Changzhi Li; Pui-In Mak; Roberto Gómez-García; Ying Chen (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications. - Changzhi Li; Ka-Fai Un; Pui-In Mak; Ying Chen; José Maria Muñoz-Ferreras; Zhi Yang 002; Roberto Gómez-García (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference. - Keith A. Bowman; Muhammad M. Khellah; Takashi Kono; Joseph Shor; Pui-In Mak (IEEE J. Solid State Circuits, 2018)

Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8-µW Steady-State Power. - Ka-Meng Lei; Pui-In Mak; Man-Kay Law; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor. - Yatao Peng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. - Gengzhen Qi; Barend van Liempd; Pui-In Mak; Rui Paulo Martins; Jan Craninckx (IEEE J. Solid State Circuits, 2018)

A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS. - Haidong Yi; Wei-Han Yu; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation. - Chak-Fong Cheang; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. - Lingshan Kong; Yong Chen 005; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency. - Xingqiang Peng; Jun Yin 001; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.032-mm2 0.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications. - Haidong Yi; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver. - Wei-Han Yu; Ka-Fai Un; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Quan Pan 002; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2019)

A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement. - Zhiyuan Chen 002; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (ISSCC, 2019)

A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (SMACD, 2019)

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA. - Zechariah Balan; Harikrishnan Ramiah; Jagadheswaran Rajendran; Nandini Vitee; Pravinah Nair Shasidharan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (Integr., 2019)

Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density. - Yang Jiang 002; Man-Kay Law; Zhiyuan Chen 002; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. - Shiheng Yang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Haidong Yi; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. - Yong Chen 005; Pui-In Mak; Zunsong Yang; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Wei Ru Wong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS. - Chao Fan; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM. - Tongquan Jiang; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM. - Chee-Cheow Lim; Harikrishnan Ramiah; Jun Yin 001; Narendra Kumar 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs. - Iat-Fai Sun; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. - Ka-Fai Un; Gengzhen Qi; Jun Yin 001; Shiheng Yang; Shupeng Yu; Chio-In Ieong; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS. - Jiangchao Wu; Ka-Chon Lei; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. - Haohong Yu; Yong Chen 005; Chirn Chye Boon; Chenyang Li 008; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 0.0018-mm2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR. - Bing Li 011; Ji-Ping Na; Wei Wang 165; Jia Liu 011; Qian Yang; Pui-In Mak (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. - Xinyi Ge; Yong Chen 005; Xiaoteng Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (CICC, 2020)

A Unity-Power-Factor Inductive Power Transfer Converter with Inherent CC-to-CV Transition Ability for Automated Guided Vehicle Charging. - Io-Wa Iam; Iok-U Hoi; Zhicong Huang; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IECON, 2020)

Low Complexity Illumination-Invariant Motion Vector Detection Based on Logarithmic Edge Detection and Edge Difference. - Chuanqi Wei; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

An N × N Multiplier-Based Multi-Bit Strong PUF using Path Delay Extraction. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

A 6.4pJ/Bit Strong Physical Unclonable Function Based on Multiple-Stage Amplifier Chain. - Jieyun Zhang; Xiaojin Zhao; Man-Kay Law; Chongyao Xu; Jiahao Liu; Pui-In Mak; Rui Paulo Martins (ISCAS, 2020)

17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3rd-Harmonic-Rich Current-Output VCO, a Harmonic-Current Filter and a 60GHz TIA. - Chao Fan; Jun Yin 001; Chee-Cheow Lim; Pui-In Mak; Rui Paulo Martins (ISSCC, 2020)

10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (ISSCC, 2020)

A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. - Yong Chen 005; Pui-In Mak; Chirn Chye Boon; Rui Paulo Martins (MWSCAS, 2020)

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2020)

Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation. - Zhiyuan Chen 002; Man-Kay Law; Pui-In Mak; Xiaoyang Zeng; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver. - Gengzhen Qi; Haijun Shao; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA. - Kai Xu; Jun Yin 001; Pui-In Mak; Robert Bogdan Staszewski; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM. - Yunbo Huang; Yong Chen 005; Hao Guo; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. - Ricardo Martins 003; Nuno Lourenço 003; Nuno Horta; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. - Ka-Fai Un; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Anding Zhu; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Cost-Effective Compensation Design for Output Customization and Efficiency Optimization in Series/Series-Parallel Inductive Power Transfer Converter. - Zhicong Huang; Zhijian Fang; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Ind. Electron., 2020)

A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. - Nandini Vitee; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2020)

An Arithmetic Progression Switched-Capacitor DC-DC Converter with Soft VCR Transitions Achieving 93.7% Peak Efficiency and 400 mA Output Current. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement. - Jixuan Li; Jiabao Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. - Xi Meng; Junqi Guo; Haoran Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Yang Jiang 002; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement. - Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ESSCIRC, 2021)

A 0.45-V 3.3-µW Resistor-Based Temperature Sensor Achieving 10mK Resolution in 65-nm CMOS. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ICTA, 2021)

A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISCAS, 2021)

A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning. - Hao Guo; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (ISSCC, 2021)

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory. - Wei-Han Yu; Massimo Giordano; Rohan Doshi; Minglei Zhang; Pui-In Mak; Rui Paulo Martins; Boris Murmann (MWSCAS, 2021)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2021)

A multi-path switched-capacitor-inductor hybrid DC-DC converter with reduced inductor loss and extended voltage conversion range. - Qiaobo Ma; Xiongjie Zhang; Yang Jiang 002; Katsuhiro Hata; Makoto Takamiya; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEICE Electron. Express, 2021)

A 12V-to-1V switched-capacitor-assisted hybrid converter with dual-path charge conduction and zero-voltage switching. - Xiongjie Zhang; Qiaobo Ma; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEICE Electron. Express, 2021)

Bird's-eye view of analog and mixed-signal chips for the 21st century. - Rui Paulo Martins; Pui-In Mak; Chi-Hang Chan; Jun Yin 001; Yan Zhu 001; Yong Chen 005; Yan Lu 002; Man-Kay Law; Sai-Weng Sin (Int. J. Circuit Theory Appl., 2021)

A 0.35-V 5, 200-μm2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2021)

A High-Efficiency Dual-Antenna RF Energy Harvesting System Using Full-Energy Extraction With Improved Input Power Response. - Zhaobo Zhang; Chenchang Zhan; Man-Kay Law; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins (IEEE Open J. Circuits Syst., 2021)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting. - Gabriel Chong; Harikrishnan Ramiah; Jun Yin 001; Jagadheswaran Rajendran; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. - Yunbo Huang; Yong Chen 005; Hailong Jiao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Startup Time and Energy-Reduction Techniques for Crystal Oscillators in the IoT Era. - Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications. - Jixuan Li; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique. - Selvakumar Mariappan; Jagadheswaran Rajendran; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers. - Selvakumar Mariappan; Jagadheswaran Rajendran; Harikrishnan Ramiah; Pui-In Mak; Jun Yin 001; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. - Jiangchao Wu; Hou-Man Leong; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

High Linearity BJT-Based Time-Domain CMOS Temperature Sensor. - Yu Lei; Qishen Fang; Jiangchao Wu; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

Adaptive Line-Transient Enhancement Techniques for Dual-Path Hybrid Converter Achieving Ultra-Low Output Overshoot/Undershoot. - Huihua Li; Qiaobo Ma; Xuchu Mu; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (APCCAS, 2022)

A 32dBm OOB-IIP3 BW-Extended 5G-NR Receiver with 4th-Order Gain-Boosted N-Path LNA. - Zhixiang Liu; Shiyou Wei; Gengzhen Qi; Pui-In Mak (APCCAS, 2022)

A 0.5 to 2GHz Blocker-Tolerant Receiver Achieving 29dBm OOB-IIP3 and 3.2 to 6dB NF Using Bottom-Plate Switched-Capacitor Technique. - Yi Mao; Yuyang Du; Yongjun He; Gengzhen Qi; Pui-In Mak (APCCAS, 2022)

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (ICECS 2022, 2022)

A Switched-Capacitor Hybrid Quadratic Buck Converter for 48V-Input Wide-Range Conversion. - Ruijie Zhao 003; Xiongjie Zhang; Xuchu Mu; Huihua Li; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (ICECS 2022, 2022)

A 108nW 0.8mm2 Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2022)

A 266µW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77dB SFDR and -3dBm OOB-B-1dB. - Haijun Shao; Pui-In Mak; Gengzhen Qi; Rui Paulo Martins (ISSCC, 2022)

Design Challenges and Considerations of Non-isolated Gate Driver for GaN-based Converters. - Xuchu Mu; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (MWSCAS, 2022)

A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. - Xinyi Ge; Yong Chen 005; Lin Wang 115; Nan Qi; Pui-In Mak; Rui Paulo Martins (NorCAS, 2022)

Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters. - Xiongjie Zhang; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (PRIME, 2022)

Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

Fully-Integrated Timers for Ultra-Low-Power Internet-of-Things Nodes - Fundamentals and Design Techniques. - Mikki How-Wen Loo; Harikrishnan Ramiah; Ka-Meng Lei; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2022)

A 108-nW 0.8-mm2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS. - Feifei Chen; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery. - Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 266-μW Bluetooth Low-Energy (BLE) Receiver Featuring an N-Path Passive Balun-LNA and a Pipeline Down-Mixing BB-Extraction Scheme Achieving 77-dB SFDR and -3-dBm OOB-B-1 dB. - Haijun Shao; Pui-In Mak; Gengzhen Qi; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 1.7-3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4-4.8 dB NF. - Haijun Shao; Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. - Xiaoteng Zhao; Yong Chen 005; Lin Wang 115; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2022)

A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (Sensors, 2022)

A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. - Peng Chen 022; Xi Meng; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. - Peng Chen 022; Jun Yin 001; Feifei Zhang; Pui-In Mak; Rui Paulo Martins; Robert Bogdan Staszewski (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank. - Hao Guo; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. - Yueduo Liu; Rongxin Bao; Zihao Zhu; Shiheng Yang; Xiong Zhou; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Power Multiband Blocker-Tolerant Receiver With a Steep Filtering Slope Using an N-Path LNA With Feedforward OB Blocker Cancellation and Filtering-by-Aliasing Baseband Amplifiers. - Haijun Shao; Gengzhen Qi; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction. - Tailong Xu; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience. - Jieyun Zhang; Chongyao Xu; Man-Kay Law; Yang Jiang 002; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-Performance Harmonic-Rich Single-Core VCO With Multi-LC Tank: A Tutorial. - Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Miniaturized Energy Harvesting Systems Using Switched-Capacitor DC-DC Converters. - Man-Kay Law; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.1-V VIN Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm2 FoM for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. - Zunsong Yang; Yong Chen 005; Jia Yuan; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Cross-Coupled Hybrid SC Converter with Extended VCR Range and Intrinsic Loss Balance Achieving 90% Average Efficiency with 1.5% Variation Over Full Li-ion Battery Input Range and 0.95A/mm2 Peak Current Density. - Qiaobo Ma; Huihua Li; Xiongjie Zhang; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (A-SSCC, 2023)

A 0.5-to-1.5GHz BW-Extended Gain-Boosted N-Path Filter Using a Switched $ mathbf{g}_{ mathbf{m}}- mathbf{C}$ Network Achieving 50MHz BW and 18.2dBm OB-IIP3. - Gengzhen Qi; Pui-In Mak (A-SSCC, 2023)

Fully Integrated Reconfigurable Solar Energy Harvester for $100 mu mathrm{A}$ Burst Output Current Delivery with 78.6% Peak Energy Extraction Efficiency and Minimum Startup Incident Light Power of 0.27mW/cm2. - Jiangchao Wu; Guangshu Zhao; Litao Zhang; Yu Jia; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man Kay Law (A-SSCC, 2023)

A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS. - Chao Fan; Ya Zhao; Yanlong Zhang; Jun Yin 001; Pui-In Mak; Guohe Zhang; Li Geng (CICC, 2023)

Simple-Logic Comparator-Offset Mitigation Technique for Resistor-Based Temperature Sensor in DFLL. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ICTA, 2023)

A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output. - Yunbo Huang; Yong Chen 005; Chaowei Yang; Pui-In Mak; Rui Paulo Martins (ISCAS, 2023)

An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $ text{FoM}_{ mathrm{T}}$. - Hao Guo; Yong Chen 005; Yunbo Huang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time. - Haihua Li; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. - Xiangxun Zhan; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (ISSCC, 2023)

A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Wei-Han Yu; Changuk Lee; Maddy Hays; Pingyu Wang; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; Youngcheol Chae; E. J. Chichilnisky; Boris Murmann; et al. (VLSI Technology and Circuits, 2023)

A 0.05-to-3.1A 585mA/mm3 97.3%-Efficiency Outphase Switched-Capacitor Hybrid Buck Converter with Relieved Capacitor Inrush Current and COUT-Free Operation. - Xiongjie Zhang; Qiaobo Ma; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Pui-In Mak; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

Design and Implementation of Hybrid DC-DC Converter: A Review. - Teck Seong Chang; Harikrishnan Ramiah; Yang Jiang 002; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Flexible Rooftop Photovoltaic-Inductive Wireless Power Transfer System for Low-Voltage DC Grid. - Io-Wa Iam; Zhaoyi Ding; Zhicong Huang; Chi-Seng Lam; Rui Paulo Martins; Pui-In Mak (IEEE Access, 2023)

Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review. - Li Fang Lai; Harikrishnan Ramiah; Tan Yee Chyan; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review. - Yi Chen Lee; Harikrishnan Ramiah; Alexander Choo Chia Chun; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Chee-Cheow Lim; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection. - Wen Xun Lian; Harikrishnan Ramiah; Gabriel Chong; Kishore Kumar Pakkirisami Churchill; Nai Shyan Lai; Saad Mekhilef; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application. - Jack Kee Yong; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Saad Mekhilef; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2023)

A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm3 Field of View. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE J. Solid State Circuits, 2023)

An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS. - Liwen Lin; Ka-Meng Lei; Pui-In Mak; Rui Paulo Martins (IEEE Open J. Circuits Syst., 2023)

A 27-dBm, 0.92-GHz CMOS Power Amplifier With Mode Switching and a High-Q Compact Inductor (HQCI) Achieving a 30% Back-Off PAE. - Arvind Singh Rawat; Jagadheswaran Rajendran; Selvakumar Mariappan; Narendra Kumar 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications. - Zhongyu Zhao; Rujian Cao; Ka-Fai Un; Wei-Han Yu; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With200 Million Training CRPs. - Chongyao Xu; Jieyun Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Inf. Forensics Secur., 2023)

A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. - Qirui Ren; Qiang Huo; Zhisheng Chen; Qi Gao; Yiming Wang; Yiming Yang; Hao Wu 084; Xiangqu Fu; Xiaoxin Xu; Qing Luo; Jianfeng Gao 005; Chengying Chen; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner. - Chao Fan; Ya Zhao; Yanlong Zhang; Jun Yin 001; Li Geng; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Bo Zhao 003; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. - Yunbo Huang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xionghui Zhou; Mei Han; Paolo Stefano Crovetti; Pui-In Mak; Rui Paulo Martins (Int. J. Circuit Theory Appl., 2023)

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. - Lin Wang 115; Yong Chen 005; Chaowei Yang; Xiaoteng Zhao; Pui-In Mak; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. - Alexander Choo Chia Chun; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Saad Mekhilef; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. - Yuchen Wei; Shiheng Yang; Yueduo Liu; Rongxin Bao; Zihao Zhu; Jiahui Lin; Zehao Zhang; Yong Chen 005; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability. - Chongyao Xu; Litao Zhang; Man-Kay Law; Xiaojin Zhao; Pui-In Mak; Rui Paulo Martins (IEEE Internet Things J., 2023)

A 0.4-V 0.0294-mm2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K2 Resolution FoM in 65-nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review. - Xuchu Mu; Guangshu Zhao; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Makoto Takamiya; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.4-V 8400-μm2 Voltage Reference in 65-nm CMOS Exploiting Well-Proximity Effect. - Chengyu Che; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting. - Alexander Choo Chia Chun; Yi Chen Lee; Harikrishnan Ramiah; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. - Kishore Kumar Pakkirisami Churchill; Harikrishnan Ramiah; Alexander Choo Chia Chun; Gabriel Chong; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM. - Jinhai Lin; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2023)

A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming. - Yunbo Huang; Yong Chen 005; Kaiyuan Yang 001; Paolo Crovetti; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs. - Qiaobo Ma; Xiongjie Zhang; Anyang Zhao; Huihua Li; Yang Jiang 002; Man-Kay Law; Makoto Takamiya; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. - Xi Meng; Haoran Li; Peng Chen 022; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices. - Jack Kee Yong; Wen Xun Lian; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Gabriel Chong; Nai Shyan Lai; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 14.7mW Blocker-Tolerant Wideband Receiver Using a Transformer-Based N-Path Passive-LNA and a 2nd-Order TIA Achieving 110MHz RF-BW and 13dBm OB-IIP3. - Gengzhen Qi; Pui-In Mak (A-SSCC, 2024)

A Miniaturized MRI Scanner Featuring a HighVoltage SOI ASIC for Non-Invasive Object Reconstruction and Flow Analysis. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (BioCAS, 2024)

A 96.7%-Efficient 2.5A Scalable DC-DC Converter Module with Complementary Dual-Mode Reconfigurable Hybrid Topology Achieving Always Inductor Current Reduction, Continuously Adjustable VCR Range, and Interleaving COUT Augmentation. - Huihua Li; Qiaobo Ma; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2024)

A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density. - Qiaobo Ma; Huihua Li; Jiahao Shi; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2024)

A 0.25pJ/Comparison, 27.3μV Input Noise Dynamic Comparator Exploiting Stacked Floating Preamplifier with Cross-Coupled Feedback Inverters in 180nm CMOS. - Jiangchao Wu; Ke Hu; Xuanlin Chen; Pui-In Mak; Rui Paulo Martins; Man Kay Law (CICC, 2024)

A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Quan Pan 002 (CICC, 2024)

A 63ns Flipping Time, 93.6% Voltage Flipping Efficiency Auto-Calibrated Ultrasonic Energy Harvesting Interface from -25 to 85°C. - Guangshu Zhao; Chao Xie; Chenxi Wang; Yang Jiang 002; Milin Zhang 001; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (CICC, 2024)

Invited Paper: A Multi-Phase Multi-Ratio Resonant Switched-Capacitor DC-DC Converter with Improved Power Density. - Jiyuan Liu; Qiaobo Ma; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (ICTA, 2024)

Quality Factor Optimization and Thermal Noise Analysis of Silicon MEMS Resonators. - Zheng Fan; Zhu Li; Renguang Tang; Guanhua Wu; Shanqing Yang; Liang Cheng Tu; Yuan Wang; Pui-In Mak (IEEE SENSORS, 2024)

17.2 A Miniature Multi-Nuclei NMR/MRI Platform with a High-Voltage SOI ASIC Achieving a 134.4dB Image SNR with a 173×250×103μm3 Resolution. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Zunsong Yang; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

3.3 A 0.5V 6.14μW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120μs] XO Startup and [8.1nJ, 200μs] Successive-Approximation-Based RTC Calibration. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

28.3 A 12-28V to 0.6-1.8V Ratio-Regulatable Dickson SC Converter with Dual-Mode Phase Misalignment Operations Achieving 93.1% Efficiency and 6A Output. - Qiaobo Ma; Yang Jiang 002; Huihua Li; Xiongjie Zhang; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

23.4 A 167 μW 71.7dB-SFDR 2.4GHz BLE Receiver Using a Passive Quadrature-Front-End, a Double-Sided Double-Balanced Cascaded Mixer and a Dual-Transformer-Coupled Class-D VCO. - Haijun Shao; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC. - Yiyang Yuan; Yiming Yang; Xinghua Wang; Xiaoran Li; Cailian Ma; Qirui Chen; Meini Tang; Xi Wei; Zhixian Hou; Jialiang Zhu; Hao Wu 084; Qirui Ren; et al. (ISSCC, 2024)

19.4 A 0.07 mm2 20-to-23.8GHz 8-phase Oscillator Incorporating Magnetic + Dual-Injection Coupling Achieving 189.2dBc/Hz FoM@10 MHz and 200.7dBc/Hz FoMA in 65nm CMOS. - Ya Zhao; Chao Fan; Qiuyu Fang; Guohe Zhang; Jun Yin 001; Pui-In Mak; Li Geng (ISSCC, 2024)

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization. - Guoqiang Xin; Fei Tan; Junde Li; Junren Chen; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (MWSCAS, 2024)

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. - Tianle Chen; Hongyu Ren; Zunsong Yang; Yunbo Huang; Xianghe Meng; Weiwei Yan; Weidong Zhang; Xuqiang Zheng; Xuan Guo; Tetsuya Iizuka; Pui-In Mak; Yong Chen 005; et al. (VLSI Technology and Circuits, 2024)

A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density. - Xuchu Mu; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (VLSI Technology and Circuits, 2024)

A Fast Startup 38.4-MHz Crystal Oscillator Achieving 99-nJ Startup Energy With Adaptive Chirping. - Abdolraouf Rahmani; Harikrishnan Ramiah; Ka-Meng Lei; Chee-Cheow Lim; Nai Shyan Lai; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2024)

Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique. - Yi Mao; Gengzhen Qi; Pui-In Mak (IEEE Open J. Circuits Syst., 2024)

A Constant-Power and Optimal-Transfer-Efficiency Wireless Inductive Power Transfer Converter for Battery Charger. - Io-Wa Iam; Chio-Kuan Choi; Chi-Seng Lam; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Ind. Electron., 2024)

Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks. - Chongyao Xu; Litao Zhang; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Inf. Forensics Secur., 2024)

A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. - Changxuan Han; Zhixian Deng; Yiyang Shu; Jun Yin 001; Pui-In Mak; Xun Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

One-Cycle-Startup Relaxation Oscillator Using Ratiometric Threshold-Referenced and Self-Synchronized Power Gating Techniques. - Guangshu Zhao; Zhiming Xiao; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time. - Haihua Li; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS. - Fei Tan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Jiahui Lin; Jun Yin 001; Qiang Li 021; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. - Hao Wu 084; Yong Chen 005; Yiyang Yuan; Jinshan Yue; Xiangqu Fu; Qirui Ren; Qing Luo; Pui-In Mak; Xinghua Wang; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial. - Tian Siang Ho; Harikrishnan Ramiah; Kishore Kumar Pakkirisami Churchill; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. - Moon Hyung Jang; Maddy Hays; Wei-Han Yu; Changuk Lee; Pietro Caragiulo; Athanasios T. Ramkaj; Pingyu Wang; A. J. Phillips; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui-In Mak; et al. (IEEE J. Solid State Circuits, 2024)

An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and COUT-Free Operations. - Xiongjie Zhang; Qiaobo Ma; Yang Jiang 002; Anyang Zhao; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 12V-to-1V Outphase-Interleaved SC Hybrid Converter With Enhanced Inductor De-Energizing Slew Rate and Adaptive Deadtime Control. - Xiongjie Zhang; Xinman Li; Anyang Zhao; Yang Jiang 002; Weihang Zhang; Jincheng Zhang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoMT in 65-nm CMOS. - Ya Zhao; Chao Fan; Yuanxing Peng; Chenglong Liang; Jun Yin 001; Pui-In Mak; Li Geng (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 93.4% Peak Efficiency CLOAD-Free Multi-Phase Switched-Capacitor DC-DC Converter Achieving a Fast DVS up to 222.5 mV/ns. - Feiyu Li; Qishen Fang; Jiangchao Wu; Yang Jiang 002; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE J. Solid State Circuits, 2024)

A 0.013 mm² 3.2-ns Input Range 10-Bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65-nm CMOS. - Xin Lu; Jiangchao Wu; Zhao Wang; Yifei Xiang; Liyuan Liu; Pui-In Mak; Rui Paulo Martins; Man-Kay Law (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics. - Xiongjie Zhang; Anyang Zhao; Qiaobo Ma; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR Loss Reduction. - Qiaobo Ma; Huihua Li; Xiongjie Zhang; Anyang Zhao; Yang Jiang 002; Man-Kay Law; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A BW-Extended Fourth-Order Gain-Boosted N-Path Filter Employing a Switched gₘ-C Network. - Gengzhen Qi; Haonan Guo; Yunchu Li; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

Miniature Magnetic Resonance Imaging System for in situ Monitoring of Bacterial Growth and Biofilm Formation. - Qi Zhou; Shuhao Fan; Ka-Meng Lei; Donhee Ham; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Biomed. Circuits Syst., 2024)

Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO. - Ya Zhao; Chao Fan; Jun Yin 001; Pui-In Mak; Li Geng (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 16-MHz Crystal Oscillator With 17.5- μ s Start-Up Time Under 104-ppm- Δ F Injection Using Automatic Phase-Error Correction. - Zixuan Wang; Xin Wang 147; Ka-Meng Lei; Wenjing Zhang; Yunjin Yin; Tailong Xu; Zhikuang Cai; Yufeng Guo; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface. - Zhizhan Yang; Jun Yin 001; Wei-Han Yu; Haochen Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization. - Yuzhao Fu; Jixuan Li; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications. - Rujian Cao; Zhongyu Zhao; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS. - Junde Li; Guoqiang Xin; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.012-mm2 0.244-pJ/bit successive approximation register analog-to-digital converter-based true random number generator for Internet of Things applications in a 65-nm complementary metal-oxide-semiconductor. - Kai Cheng; Yong Chen 005; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2024)

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO. - Haijun Shao; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 30-110V Resonant Buck-Boost Power-Bus Charger Achieving 50-A Peak Laser-Current Pulse Generation in 2ns for MHz-Frequency Automotive LiDAR Transmitter. - Hangxiao Ma; Qiaobo Ma; Xuchu Mu; Yang Jiang 002; Rui Paulo Martins; Pui-In Mak (CICC, 2025)

A 98.5% Peak Efficiency 2/3-Phase Buck-or-Boost Converter With VCR-Independent Loss Optimization and Unconditional RHP Zero Elimination Achieving 2.76A/mm2-Current-Density and 6.5µs Recovery. - Xiongjie Zhang; Xinman Li; Yang Jiang 002; Zhangming Zhu; Rui Paulo Martins; Pui-In Mak (CICC, 2025)

A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS. - Yantong Liu; Fei Tan; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (CNIOT, 2025)

A Linear-Regression-Assisted Trimming Scheme for CMOS Voltage Reference. - Chengyu Che; Yao Jiang; Xinfei Guo; Ka-Meng Lei; Rui Martins; Pui-In Mak (ISCAS, 2025)

A BW-Extended Multi-Band Receiver with High-Order N-Path Filtering at RF Front-End and BB Achieving 200MHz BW and 36.5dBm OB-IIP3. - Gengzhen Qi; Yunchu Li; Shaolin Liao; Pui-In Mak (ISCAS, 2025)

A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates. - Zhizhan Yang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISCAS, 2025)

A 0.4V Relaxation Oscillator featuring Double Capacitor-Charging Headroom in CMOS 65nm. - Kanghong Yu; Mingrui Wang; Ka-Meng Lei; Rui Martins; Pui-In Mak (ISCAS, 2025)

A Chip-based Miniature MRI Platform with Integrated PDMS-PCB Coil Frontend for Microlitre-volume Sample Analysis. - Qi Zhou; Shuhao Fan; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISCAS, 2025)

19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD. - Haoran Li; Jinge Li; Xueying Jiang; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C. - Yueduo Liu; Zihao Zhu; Xinyu Yang; Rongxin Bao; Zehao Zhang; Hongshuai Zhang; Jiaxin Liu; Zheng Wang; Mingkang Zhang; Na Yan; Jun Yin 001; Pui-In Mak; et al. (ISSCC, 2025)

27.5: A 4, 100µm2 Wire-Metal-Based Temperature Sensor with a Fractional-Discharge FLL and a Time-Domain Amplifier with ±0.2°C Inaccuracy (3σ) from -40 to 125°C and 45fJ·K2 Resolution FoM in 28nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference. - Yiyang Yuan; Bingxin Zhang; Yiming Yang; Yishan Luo; Qirui Chen; Shidong Lv; Hao Wu 084; Cailian Ma; Ming Li; Jinshan Yue; Xinghua Wang; Guozhong Xing; et al. (ISSCC, 2025)

A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. - Haochen Zhang; Wei-Han Yu; Zhongyu Zhao; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation. - Margarida Lourenço; Bingbing Zhao; Junde Li; Marcelino B. Santos; Pui-In Mak; Rui Paulo Martins; Wei-Han Yu; Fábio Passos (SMACD, 2025)

A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. - Haochen Zhang; Wei-Han Yu; Zhizhan Yang; Ka-Fai Un; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. - Xiangxun Zhan; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor. - Chaowei Yang; Yong Chen 005; Kai Cheng; Paolo Stefano Crovetti; Rui Paulo Martins; Pui-In Mak (Int. J. Circuit Theory Appl., 2025)

A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM. - Fei Tan; Wei-Han Yu; Jinhai Lin; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification. - Zhizhan Yang; Haochen Zhang; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 0.35-0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS. - Dan Shi; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications. - Chen Deng; Sai Wu; Chengcheng Liu; Yatao Peng; Man-Kay Law; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow. - Yi Zhan; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From -40 °C to 125 °C. - Rui Luo; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm. - Fei Tan; Yujia Wang; Wei-Han Yu; Ka-Fai Un; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA. - Ya Zhao; Lingao Huang; Runchen Wang; Jun Yin 001; Pui-In Mak; Li Geng; Chao Fan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer. - Tan Yee Chyan; Harikrishnan Ramiah; Sharifah Wan Muhamad Hatta; Chee-Cheow Lim; Rui Paulo Martins; Pui-In Mak; Yong Chen 005 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Miniature Multinuclei NMR/MRI Platform With a High-Voltage SOI ASIC. - Shuhao Fan; Qi Zhou; Ka-Meng Lei; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL. - Jingrun Song; Xinyu Yang; Jiaxu Liu; Yueduo Liu; Zihao Zhu; Zhengxuan Han; Zehao Zhang; Jiaxin Liu; Hongshuai Zhang; Jun Yin 001; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2025)

A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization. - Jixuan Li; Ke Li; Ka-Fai Un; Wei-Han Yu; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Rui Paulo Martins; Pui-In Mak; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)