A multi-story power delivery technique for 3D integrated circuits. - Pulkit Jain; Tony Tae-Hyoung Kim; John Keane 001; Chris H. Kim (ISLPED, 2008)

Enhancing beneficial jitter using phase-shifted clock distribution. - Dong Jiao; Jie Gu 003; Pulkit Jain; Chris H. Kim (ISLPED, 2008)

A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISLPED, 2009)

Logic-compatible embedded DRAM design for memory intensive low power systems. - Ki Chul Chun; Pulkit Jain; Chris H. Kim (ISCAS, 2010)

A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (ISSCC, 2011)

A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches. - Ki Chul Chun; Pulkit Jain; Jung-Hwa Lee; Chris H. Kim (IEEE J. Solid State Circuits, 2011)

An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs. - Pulkit Jain; John Keane 001; Chris H. Kim (ESSDERC, 2012)

A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor. - Ki Chul Chun; Wei Zhang 032; Pulkit Jain; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches. - Ki Chul Chun; Pulkit Jain; Tae-Ho Kim; Chris H. Kim (IEEE J. Solid State Circuits, 2012)

Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design. - Xiaofei Wang; John Keane 001; Tony Tae-Hyoung Kim; Pulkit Jain; Qianying Tang; Chris H. Kim (IEEE Micro, 2014)

The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications. - Xiaofei Wang; Qianying Tang; Pulkit Jain; Dong Jiao; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. - Pulkit Jain; Umut Arslan; Meenakshi Sekhar; Blake C. Lin; Liqiong Wei; Tanaya Sahu; Juan Alzate-vinasco; Ajay Vangapaty; Mesut Meterelliyoz; Nathan Strutt; Albert B. Chen; Patrick Hentges; et al. (ISSCC, 2019)

A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. - Liqiong Wei; Juan G. Alzate; Umut Arslan; Justin Brockman; Nilanjan Das; Kevin Fischer; Tahir Ghani; Oleg Golonzka; Patrick Hentges; Rawshan Jahan; Pulkit Jain; Blake C. Lin; et al. (ISSCC, 2019)

16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing. - Shanshan Xie; Can Ni; Aseem Sayal; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (ISSCC, 2021)

GNC Analysis and Robotic Systems Configuration of Collision-free Earth Observation Satellites (CfEOS) Constellations. - Manuel Ntumba; Saurabh Gore; Pulkit Jain; Jean-Baptiste Awanyo (CoRR, 2021)

Development of a Model for Review Sharing in the Context of Mobile Phone Purchase Amongst Indian Millennials. - Som Sekhar Bhattacharyya; Sumi Jha; Shubham Khandelwal; Pulkit Jain; Anshul Ekka (Int. J. Asian Bus. Inf. Manag., 2021)

Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. - Shanshan Xie; Can Ni; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (VLSI Technology and Circuits, 2022)

Design and Implementation of a Quantitative Network Health Monitoring and Recovery System. - Harshit Gujral; Abhinav Sharma; Pulkit Jain; Shriya Juneja; Sangeeta Mittal (Wirel. Pers. Commun., 2022)

eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters. - Shanshan Xie; Can Ni; Aseem Sayal; Pulkit Jain; Fatih Hamzaoglu; Jaydeep P. Kulkarni (IEEE J. Solid State Circuits, 2024)