Circuit and DFT techniques for robust and low cost qualification of a mixed-signal SoC with integrated power management system. - Lakshmanan Balasubramanian; Puneet Sabbarwal; Rajesh Kumar Mittal; Prakash Narayanan; Ranjit Kumar Dash; Anand Devendra Kudari; Srikanth Manian; Sudhir Polarouthu; Harikrishna Parthasarathy; Ravi C. Vijayaraghavan; Sachin Turkewadikar (DATE, 2011)

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. - Rajesh Mittal; Lakshmanan Balasubramanian; Adesh Sontakke; Harikrishna Parthasarathy; Prakash Narayanan; Puneet Sabbarwal; Rubin A. Parekhji (ITC, 2011)

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. - Prakash Narayanan; Rajesh Mittal; Sumanth Poddutur; Vivek Singhal; Puneet Sabbarwal (VTS, 2011)