Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance. - Markus Dietl; Puneet Sareen (NESEA, 2010)

A new low power and area efficient semi-digital PLL architecture for low bandwidth applications. - Markus Dietl; Puneet Sareen (ACM Great Lakes Symposium on VLSI, 2011)

Very high bandwidth semi-digital PLL with large operating frequency range. - Vivek Elangovan; Markus Dietl; Puneet Sareen (NORCHIP, 2011)

A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter. - Mitesh Yogesh; Puneet Sareen; Markus Dietl; Ketan Dewan (NORCHIP, 2012)

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter. - S. Fahmy; Markus Dietl; Puneet Sareen; Maurits Ortmanns; Jens Anders (NORCAS, 2015)

A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS. - Jens Anders; Sebastian Bader 003; Markus Dietl; Puneet Sareen; G. Rombach; Sotirios Tambouris; Maurits Ortmanns (A-SSCC, 2017)