Efficient implementation of 90° phase shifter in FPGA. - Punithavathi Duraiswamy; Johan Bauwelinck; Jan Vandewege (EURASIP J. Adv. Signal Process., 2011)

Synchronous delay based UWB pulse generator in FPGA. - Punithavathi Duraiswamy; Xiao Li; Johan Bauwelinck; Jan Vandewege; Peter Vaes; Stephanie Teughels (IEICE Electron. Express, 2012)

Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications. - Punithavathi Duraiswamy; Satishkumar; Raghu; Shankar Kumar Selvaraja (IEICE Electron. Express, 2020)

Single Stage Low Noise Inductor-Less TIA for RF Over Fiber Communication. - Vijay Kumar 007; G. Sai Saravanan; Punithavathi Duraiswamy; Shankar Kumar Selvaraja (IEEE Access, 2021)

GA Evolved Configuration Data for Embryonic Architecture with Built-in Self-test. - Gayatri Malhotra; Punithavathi Duraiswamy; J. K. Kishore (ISDA (1), 2022)

GA evolved CGP configuration data for digital circuit design on embryonic architecture. - Gayatri Malhotra; Punithavathi Duraiswamy (Int. J. Hybrid Intell. Syst., 2023)