Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study. - S. Ramesh 001; Purandar Bhaduri (CAV, 1999)

An Application of Compiler Technology to the Year 2000 Problem. - Mangala Gowri Nanda; Purandar Bhaduri; Sundeep Oberoi; Amitabha Sanyal (Softw. Pract. Exp., 1999)

Formalizing Models and Meta-models for System Development. - R. Venkatesh; Purandar Bhaduri; Mathai Joseph (APSEC, 2001)

Formal Techniques for Analysing Scenarios using Message Sequence Charts. - Purandar Bhaduri; R. Venkatesh; Girish Keshav Palshikar (VISS@ETAPS, 2002)

Model Checking Visual Specification of Requirements. - Ulka Shrotri; Purandar Bhaduri; R. Venkatesh 001 (SEFM, 2003)

Verification of Scenario-based Specifications using Templates. - Girish Keshav Palshikar; Purandar Bhaduri (SVV@ICLP, 2003)

Model Checking of Statechart Models: Survey and Research Directions - Purandar Bhaduri; S. Ramesh (CoRR, 2004)

Synthesis of Interface Automata. - Purandar Bhaduri (ATVA, 2005)

Synthesis of Synchronous Interfaces. - Purandar Bhaduri; S. Ramesh 001 (ACSD, 2006)

Verification of Giotto based Embedded Control Systems. - Rajiv Kumar Poddar; Purandar Bhaduri (Nord. J. Comput., 2006)

Modeling Fixed Priority Non-Preemptive Scheduling with Real-Time Calculus. - Devesh B. Chokshi; Purandar Bhaduri (RTCSA, 2008)

Interface synthesis and protocol conversion. - Purandar Bhaduri; S. Ramesh (Formal Aspects Comput., 2008)

A proposal for real-time interfaces in SPEEDS. - Purandar Bhaduri; Ingo Stierand (DATE, 2010)

Performance analysis of FlexRay-based systems using real-time calculus, revisited. - Devesh B. Chokshi; Purandar Bhaduri (SAC, 2010)

Performance analysis of IEEE 802.11 IBSS power save mode using a discrete-time markov model. - Pravati Swain; Sandip Chakraborty 001; Sukumar Nandi; Purandar Bhaduri (SAC, 2012)

Characterizing feedback signal drop patterns in formal verification of networked control systems. - Dip Goswami; Samarjit Chakraborty; Purandar Bhaduri; Sanjoy K. Mitter (CACSD, 2013)

Real-time scheduling interfaces and contracts for the design of distributed embedded systems. - Ingo Stierand; Philipp Reinkemeier; Tayfun Gezgin; Purandar Bhaduri (SIES, 2013)

Virtual Integration of Real-Time Systems Based on Resource Segregation Abstraction. - Ingo Stierand; Philipp Reinkemeier; Purandar Bhaduri (FORMATS, 2014)

Performance modeling and evaluation of IEEE 802.11 IBSS power save mode. - Pravati Swain; Sandip Chakraborty 001; Sukumar Nandi; Purandar Bhaduri (Ad Hoc Networks, 2014)

Probabilistic model checking of IEEE 802.11 IBSS power save mode. - Pravati Swain; Purandar Bhaduri; Sukumar Nandi (Int. J. Wirel. Mob. Comput., 2014)

Reconfigurable Communication Middleware for Flex Ray-Based Distributed Embedded Systems. - Diptesh Majumdar; Licong Zhang; Purandar Bhaduri; Samarjit Chakraborty (RTCSA, 2015)

Performance Modeling and Analysis of IEEE 802.11 IBSS PSM in Different Traffic Conditions. - Pravati Swain; Sandip Chakraborty 001; Sukumar Nandi; Purandar Bhaduri (IEEE Trans. Mob. Comput., 2015)

Translation Validation of Loop Invariant Code Optimizations Involving False Computations. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (VDAT, 2017)

Axiomatization of if-then-else over monoids of possibly non-halting programs and tests. - Gayatri Panicker; Kanduru V. Krishna; Purandar Bhaduri (CoRR, 2017)

Axiomatization of if-then-else over possibly non-halting programs and tests. - Gayatri Panicker; Kanduru V. Krishna; Purandar Bhaduri (Int. J. Algebra Comput., 2017)

Time-Triggered Scheduling of Mixed-Criticality Systems. - Lalatendu Behera; Purandar Bhaduri (ACM Trans. Design Autom. Electr. Syst., 2017)

Time-Triggered Scheduling for Multiprocessor Mixed-Criticality Systems. - Lalatendu Behera; Purandar Bhaduri (ICDCIT, 2018)

On the structure of C-algebras through atomicity and if-then-else. - Gayatri Panicker; Kanduru V. Krishna; Purandar Bhaduri (CoRR, 2018)

Formal Verification of Optimizing Transformations during High-level Synthesis. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (ISEC, 2019)

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (VLSID, 2019)

Counter-example generation procedure for path-based equivalence checkers. - Ramanuj Chouksey; Chandan Karfa; Kunal Banerjee 001; Pankaj Kumar Kalita; Purandar Bhaduri (IET Softw., 2019)

Translation Validation of Code Motion Transformations Involving Loops. - Ramanuj Chouksey; Chandan Karfa; Purandar Bhaduri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An energy-efficient time-triggered scheduling algorithm for mixed-criticality systems. - Lalatendu Behera; Purandar Bhaduri (Des. Autom. Embed. Syst., 2020)

Coalgebras for Bisimulation of Weighted Automata over Semirings. - Purandar Bhaduri (Log. Methods Comput. Sci., 2023)

The Complexity of Pure Strategy Relevant Equilibria in Concurrent Games. - Purandar Bhaduri (CoRR, 2025)